US4462029A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Command bus
Assignee: Analogic Corp
•
Filing: 1979-12-06
•
Granted: 1984-07-24
•
Expires: 1999-12-06
Abstract
Abstract A system for reducing a fixed number of data buses and connections in a computer system having a number of modules connected to the data bus utilizing the internal circuits of the various processing units or modules to transmit data from one unit to another via the data bus when the normal function of a unit can be interrupted, with the data routing and module control being under the control of a command bus.
Inventors
- 👤 Leopold Neumann
- 👤 Gerald N. Shapiro
- 👤 Bruno A. Mattedi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 21:06
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4027; G06F11/00; G06F11/22; G06F13/14; G06F13/36; G06F13/362; G06F13/364
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
256 words
In a computer system which includes a number of modules which perform normal data processing functions, said system including a number of parallel data buses, each with a number of lines, with each module connected to at least one data bus via the lines thereof, each of said modules having at least one register; a command bus connected to each of said modules, said command bus adapted to carry commands in the form of digital coding for either interrupting this normal data processing function of a module and for establishing a switching function, or for reading out the contents of a register in an associated module; means within selected modules for generating said commands; means for establishing priority of said commands and for placing said command on said command bus in accordance with the established priority; and means within more than one predetermined module responsive to a command placed on said command bus for interrupting the normal data processing function of the associated module to transform it into a nonprocessor switch for either establishing a switching function in which a connection path determined by said command is established between the lines of a first and second one of said parallel data buses to permit switching of data from the lines of one data bus to the lines of another in which there is a nonprocessor transfer of data, with no data being processed in the switching operation, of for reading out the contents of a register in said associated module to a temporarily unused data bus.
Claim 2
Dependent Claim
256 words
In a computer system which includes a number of modules which perform normal data processing functions, said system including a number of parallel data buses, each with a number of lines, with each module connected to at least one data bus via the lines thereof, each of said modules having at least one register; a command bus connected to each of said modules, said command bus adapted to carry commands in the form of digital coding for either interrupting this normal data processing function of a module and for establishing a switching function, or for reading out the contents of a register in an associated module; means within selected modules for generating said commands; means for establishing priority of said commands and for placing said command on said command bus in accordance with the established priority; and means within more than one predetermined module responsive to a command placed on said command bus for interrupting the normal data processing function of the associated module to transform it into a nonprocessor switch for either establishing a switching function in which a connection path determined by said command is established between the lines of a first and second one of said parallel data buses to permit switching of data from the lines of one data bus to the lines of another in which there is a nonprocessor transfer of data, with no data being processed in the switching operation, of for reading out the contents of a register in said associated module to a temporarily unused data bus.
Claim 3
Dependent Claim
29 words
The system of claim 1 wherein said priority establishing means includes means for placing a normal code on said command bus when no commands are generated within a module.
Claim 4
Dependent Claim
27 words
The system of claim 1 wherein said predetermined modules are taken from a group consisting of a controller, a host computer interface and/or a side door interface.
Claim 5
Dependent Claim
14 words
The system of claim 1 wherein each of said modules includes a decoding unit.
Claim 6
Dependent Claim
20 words
The system of claim 1 wherein each of said decoding units includes a PROM, and a latch circuit coupled thereto.
Claim 7
Dependent Claim
18 words
The system of claim 1 wherein said interrupting means includes means for freezing the operation of said register.
Claim 8
Dependent Claim
57 words
The system of claim 1 wherein said means for establishing a predetermined connection path includes a bidirectional gate, the direction of which is specified by commands on said command bus, input/output terminals at the corresponding modules connected to said first and second data buses, and means for connecting said bidirectional gate to bridge across said input/output terminals.
Claim 9
Dependent Claim
82 words
The system of claim 1 wherein said last mentioned means includes a buffer coupled to said first data bus; means for selecting between signals on said first data bus and the output of said buffer; a register coupled to the output of said selecting means; unidirectional gate means for selectively coupling the output of said register to said first bus; bidirectional gate means for selectively coupling said first and second data buses together, and means for freezing the output of said register.
Claim 10
Dependent Claim
14 words
The system of claim 1 wherein said fixed number of data buses is four.
Claim 11
Dependent Claim
34 words
The system of claim 9 wherein said four data buses normally function respectively as a controller information bus, an arithmetic unit memory bus, a host computer input/output bus and a side door outside bus.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-07-24 | 1988-01-23 | 1988-07-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-07-24 | 1992-01-23 | 1992-07-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-07-24 | 1996-01-23 | 1996-07-24 | $7700.00 | Window Closed / Lapsed |