US4462004A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dynamic class-4 FET amplifier
Assignee: Nokia Bell Labs
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Filing: 1982-03-18
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Granted: 1984-07-24
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Expires: 2002-03-18
Abstract
Abstract The present invention relates to a linear, class A FET amplifier circuit capable of providing linear amplifier of input signals with a time-varying envelope function. An envelope detector (12) is responsive to an input signal (v i (t)) for extracting the envelope signal (V i (t)) therefrom. A gate controller (16) subsequently adds the envelope signal to a predetermined gate bias voltage (E G ) and applies the sum (E G (t)) as the "d-c" gate input to the FET amplifier (14). Therefore, the gate bias voltage is dynamically controlled by the envelope of the input signal, resulting in a significant improvement in the power-added efficiency (η added ) over prior art class A FET amplifiers.
Inventors
- 👤 Donald C. Cox
- 👤 Adel A. M. Saleh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:58
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/02; H03F1/0205; H03F1/0261; H03F1/0266; H03F2200/00; H03F2200/102; H03F2200/18; H03F2200/192
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
230 words
A field-effect-transistor (FET) amplifier circuit responsive to a time-varying input signal (v i (t)) for operating in a linear, class A mode and producing as an output an amplified time-varying output signal (v o (t)), wherein said FET amplifier circuit comprises an FET amplifier (14) including a source input terminal, a drain input terminal, a gate input terminal, and an output terminal for receiving an input signal at said source input terminal and producing an amplified version thereof at said output terminal; a drain bias voltage source (18) for producing as an output a drain bias voltage signal (E D ) which is coupled to said drain input terminal of said FET amplifier; a capacitor (20) disposed between the output of said drain bias voltage source and a ground plane for removing time variations in a current from said drain bias voltage source; envelope detecting means (12) responsive to said time-varying input signal for producing as an output an envelope signal (V i (t)) related to said time-varying input signal; and a gate bias voltage source (16) responsive to both a predetermined constant gate voltage (E Go ) and said envelope signal produced by said envelope detecting means for producing as an output a gate control signal (E G (t)) equal to the sum thereof, said gate control signal subsequently coupled to said gate input terminal of said FET amplifier.
Claim 2
Dependent Claim
230 words
A field-effect-transistor (FET) amplifier circuit responsive to a time-varying input signal (v i (t)) for operating in a linear, class A mode and producing as an output an amplified time-varying output signal (v o (t)), wherein said FET amplifier circuit comprises an FET amplifier (14) including a source input terminal, a drain input terminal, a gate input terminal, and an output terminal for receiving an input signal at said source input terminal and producing an amplified version thereof at said output terminal; a drain bias voltage source (18) for producing as an output a drain bias voltage signal (E D ) which is coupled to said drain input terminal of said FET amplifier; a capacitor (20) disposed between the output of said drain bias voltage source and a ground plane for removing time variations in a current from said drain bias voltage source; envelope detecting means (12) responsive to said time-varying input signal for producing as an output an envelope signal (V i (t)) related to said time-varying input signal; and a gate bias voltage source (16) responsive to both a predetermined constant gate voltage (E Go ) and said envelope signal produced by said envelope detecting means for producing as an output a gate control signal (E G (t)) equal to the sum thereof, said gate control signal subsequently coupled to said gate input terminal of said FET amplifier.
Claim 3
Dependent Claim
95 words
An FET amplifier circuit formed in accordance with claim 1 wherein said FET amplifier circuit further comprises a directional coupler (10) responsive to the time-varying input signal for producing a first large magnitude output signal and a second small magnitude output signal, where the sum of said first and said second output signals is equal to the magnitude of said time-varying input signal, said first large magnitude output signal coupled to the source input terminal of said FET amplifier and said second small magnitude output signal applied as the input to the envelope detecting means.
Claim 4
Dependent Claim
40 words
An FET amplifier circuit formed in accordance with claim 2 wherein the second small magnitude output signal of the directional coupler is of a value between approximately 10 dB and approximately 20 dB less than the time-varying input signal level.
Claim 5
Dependent Claim
53 words
An FET amplifier circuit formed in accordance with claim 1 wherein the predetermined constant gate voltage is equal to a negative value of a predetermined pinch-off voltage (V P ) of said FET amplifier and the drain bias voltage is equal to one-half of a predetermined maximum allowable drain voltage (V m ).
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-07-24 | 1988-01-23 | 1988-07-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-07-24 | 1992-01-23 | 1992-07-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-07-24 | 1996-01-23 | 1996-07-24 | $7700.00 | Window Closed / Lapsed |