Carrier regenerating circuit

Claim 2

In a carrier regenerating circuit of the type having a first signal path, including a first band pass filter, for regenerating a first carrier signal from a received M-phase shift keying (PSK) signal, where M is an integer greater than one, the improvement comprising: a second signal path, including a second band pass filter having a narrower band width band than said first band pass filter for generating a second carrier signal from said PSK signal; phase comparison means for phase comparing said first and second regenerated carriers; and variable phase shift means for receiving said first regenerated carrier signal and shifting the phase thereof in accordance with the results of said phase comparison.

Claim 3

A carrier regenerating circuit as defined in claim 1, wherein said first signal further includes a first multiplier for multiplying the frequency of said received signal by M and providing a frequency multiplied signal to an input of said first band pass filter, and a first divider for dividing the frequency of an output of said first band pass filter by M; and wherein said second band pass filter receives its input from said first multiplier and said second signal path further includes a second divider for dividing the output frequency of said second band pass filter by M.

Claim 4

A carrier regenerating circuit as defined in claim 1, wherein said phase comparison means comprises: a first phase shifter for phase advancing said second regenerated carrier; a second phase shifter for phase retarding said second regenerated carrier; a first mixer for phase comparing the output of said variable phase shifter with said phase advanced signal; a second mixer for phase comparing the output of said variable phase shifter with said phase retarded signal; and logic circuitry responsive to phase comparison results of said first and second mixers for controlling said variable phase shifter in response thereto.

Claim 5

A carrier regenerating circuit as defined in claim 3, wherein said phase comparison means further comprises a first low pass filter for receiving the output from said first mixer and providing a first phase comparison signal in response thereto, and a second low pass filter for receiving said output of said second mixer and providing a second phase comparison signal in response thereto, wherein said logic circuitry comprises: first analog-to-digital (A/D) conversion means for converting said first phase comparison signal to digital form; second A/D conversion means for converting said second phase comparison signal to digital form; a source of clock pulses; and an up/down counter for counting said clock pulses in a direction determined by the outputs of said first and second A/D conversion means, the count value in said counter controlling said variable phase shift means.

Claim 6

A carrier regenerating circuit as defined in any one of claims 3-4, wherein said variable phase shifter comprises a multiple-stage shift register and means responsive to an output signal from said logic circuitry for selecting an output from one of said shift register stages.

Claim 7

A carrier regenerating circuit according to any one of claims 1 and 2-4, wherein said phase comparison means receives said first regenerated carrier from the output of said variable phase shift means.

Claim 8

A carrier regenerating circuit as defined in any one of claims 1 and 2-4, wherein said phase comparison means receives said first regenerated carrier from the input to said variable phase shift means.