US4461013A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Frequency modulation transmitter for voice or data
Assignee: Nokia Bell Labs
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Filing: 1982-12-06
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Granted: 1984-07-17
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Expires: 2002-12-06
Abstract
Abstract A portable frequency modulation transmitter (1) for voice or data is disclosed for operation at infrared frequencies. The transmitter comprises keyboard (200) or microphone (402) input capability and dual modes of use. In the data mode, carrier is generated when the keyboard is operated and is not generated when the keyboard is idle in order to conserve power. In the voice mode, either voice or data may be transmitted, data having priority over voice. A series connection of two variable modulus counters (302, 303) and other counters (304, 305, 306) provide a frequency shift keyed data signal, marker data signal, marker data frames between data frames, parity insertion and other features. In the event that the local battery power level falls below a particular level, a particular word is inserted in the applied binary data input.
Inventors
- 👤 Gregory Lese
- 👤 Donald H. Nash
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 21:44
CPC Classifications
H; H04; H04B; H04B10/00; H04B10/50; H03; H03J; H03J9/00; H03J9/06; H04M; H04M11/00; H04M11/06; H04M11/066; H04M11/08; H04M11/085
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
147 words
A frequency shift keyed signal generator circuit characterized by a first variable modulus counter (302) for dividing a clock frequency by a particular first or second modulus (M or N), an applied input (A) being a binary zero or one data signal respectively, the output being a frequency shift keyed signal (B), a second variable modulus counter (303), responsive to the applied input signal (A) and the frequency shift keyed output signal (B) of the first variable modulus counter (302), for dividing the frequency shift keyed output signal by the predetermined second or first modulus (N or M), the output (C) being at the bit rate of the applied input signal (A), and a data bit counter (304), responsive to the output of the second variable modulus counter (303), for dividing the output of the second variable modulus counter by a particular binary quantity of data bits.
Claim 2
Dependent Claim
147 words
A frequency shift keyed signal generator circuit characterized by a first variable modulus counter (302) for dividing a clock frequency by a particular first or second modulus (M or N), an applied input (A) being a binary zero or one data signal respectively, the output being a frequency shift keyed signal (B), a second variable modulus counter (303), responsive to the applied input signal (A) and the frequency shift keyed output signal (B) of the first variable modulus counter (302), for dividing the frequency shift keyed output signal by the predetermined second or first modulus (N or M), the output (C) being at the bit rate of the applied input signal (A), and a data bit counter (304), responsive to the output of the second variable modulus counter (303), for dividing the output of the second variable modulus counter by a particular binary quantity of data bits.
Claim 3
Dependent Claim
128 words
A frequency shift keyed signal generator circuit characterized by means (302) for dividing a clock frequency by a particular first or second modulus (M or N), an applied input (A) being a binary zero or one data signal respectively, the output being a frequency shift keyed signal (B), means (303), responsive to the applied input signal (A) and the frequency shift keyed signal (B), for dividing the frequency shift keyed signal by the predetermined second or first modulus (N or M), the output (C) being at the bit rate of the applied input signal (A), and means (304), responsive to the output (C) of the second variable modulus counter (303), for dividing the output of the second variable modulus counter by a particular binary quantity of data bits.
Claim 4
Dependent Claim
128 words
A frequency shift keyed signal generator circuit characterized by means (302) for dividing a clock frequency by a particular first or second modulus (M or N), an applied input (A) being a binary zero or one data signal respectively, the output being a frequency shift keyed signal (B), means (303), responsive to the applied input signal (A) and the frequency shift keyed signal (B), for dividing the frequency shift keyed signal by the predetermined second or first modulus (N or M), the output (C) being at the bit rate of the applied input signal (A), and means (304), responsive to the output (C) of the second variable modulus counter (303), for dividing the output of the second variable modulus counter by a particular binary quantity of data bits.
Claim 5
Dependent Claim
58 words
A frequency shift keyed signal generator circuit as recited in claim 1 or 2 further characterized by a data selector circuit (301), for inserting a flip bit in the applied binary data input (A), the flip bit for assisting a receive terminal to distinguish between a break in data transmission and a multiple transmission of the same data.
Claim 6
Dependent Claim
38 words
A frequency shift keyed signal generator circuit as recited in claim 3 further characterized in that the data selector circuit (301) additionally inserts a parity bit, dependent on the flip bit, in the applied binary data input (A).
Claim 7
Dependent Claim
50 words
A frequency shift keyed signal generator circuit as recited in claim 1 further characterized by a low battery indicating circuit (203, 212, 213, 301), responsive to a control signal indicating a low battery condition, for inserting a particular code for the low battery condition in the applied binary data input.
Claim 8
Dependent Claim
51 words
A frequency shift keyed signal generator circuit as recited in claim 5 further characterized in that the low battery indicating circuit comprises a low battery code inhibit circuit (203), responsive to a data signal, for inhibiting the insertion of the particular low battery code in the presence of the data signal.
Claim 9
Dependent Claim
37 words
A frequency shift keyed signal generator circuit as recited in claim 1 further characterized by a data selector circuit (301) for inserting a flip bit having a particular periodic location in the applied binary data input (A).
Claim 10
Dependent Claim
49 words
A frequency shift keyed signal generator circuit as recited in claim 1 further characterized by a marker data counter (305), responsive to the data bit counter (304), for providing a control signal (G) to the first variable modulus counter (302), the control signal regulating the provision of marker data.
Claim 11
Dependent Claim
24 words
A frequency shift keyed signal generator circuit as recited in claim 8 further characterized by a frame counter (306), responsive to the marker/data counter.
References Cited (Backward Citations)
US3761625A
Cited
US4232308A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-07-17 | 1988-01-16 | 1988-07-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-07-17 | 1992-01-16 | 1992-07-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-07-17 | 1996-01-16 | 1996-07-17 | $7700.00 | Window Closed / Lapsed |