Memory cell

Claim 2

A non-volatile memory cell, said memory cell comprising: a series combination of a fixed threshold switching means and of an essentially variable threshold switching means each having first and second terminating regions and a control region therein by which each is capable of being directed to effectively provide a conductive path of a selected conductivity between said first and second terminating regions therein, said essentially variable threshold switching means control region being electrically isolated from said essentially variable threshold switching means first and second terminating regions to prevent, at sufficiently small voltages thereacross, any electrical currents from traversing between said essentially variable threshold switching means control region and either of said first and second terminating regions of said essentially variable threshold switching means, said fixed threshold switching means first terminating region being electrically connected to a first terminal means adapted for electrical connection to a first selection means, said fixed threshold switching means control region being electrically connected to a second terminal means adapted for electrical connection to a second selection means, said fixed threshold switching means second terminating region being electrically connected to said essentially variable threshold switching means first terminating region, and said essentially variable threshold switching means second terminating region being electrically connected to a third terminal means adapted for electrical connection to a third selection means; a tunneling capacitance means having first and second polarity regions partially electrically isolated from one another to prevent, at sufficiently small voltages therebetween, any significant electrical currents from traversing between said tunneling capacitance means first and second polarity regions but to permit significant electrical currents to traverse between said tunneling capacitance means first and second polarity regions at larger voltages though these be voltages which are still sufficiently small to prevent electrical currents from traversing between said essentially variable threshold switching means control region and either of said first or second terminating regions of said essentially variable threshold switching means, said tunneling capacitance means second polarity region being electrically connected to said essentially variable threshold switching means control region; a coupling capacitance means having first and second polarity regions electrically isolated from one another to prevent any electrical currents from traversing between said coupling capacitance means first and second polarity regions, at voltages therebetween similar to those for which electrical isolation is maintained between said essentially variable threshold switching means control region and said essentially variable threshold switching means first and second terminating regions as aforesaid, said coupling capacitance means first polarity region being electrically connected to a fourth terminal means adapted for electrical connection to a fourth selection means, and said coupling capacitance means second polarity region being electrically connected to said essentially variable threshold switching means control region; and a control switching means having first and second terminating regions and a control region therein by which said control switching means is capable of being directed to effectively provide a conductive path of a selected conductivity between said control switching means first and second terminating regions, said control switching means first terminating region being electrically connected to a fifth terminal means adapted for electrical connection to a fifth selection means, said control switching means control region being electrically connected to a sixth terminal means adapted for electrical connection to a sixth selection means, and said control switching means second terminating region being electrically connected to said tunneling capacitance means first polarity region.

Claim 3

The apparatus of claim 1 wherein said first terminal means and said fifth terminal means are electrically interconnected and said first selection means and said fifth selection means are a common selection means.

Claim 4

The apparatus of claim 1 wherein said second terminal means and said sixth terminal means are electrically interconnected and said second selection means and said sixth selection means are a common selection means.

Claim 5

The apparatus of claim 1 wherein said fifth terminal means and said sixth terminal means are electrically interconnected and said fifth selection means and said sixth selection means are a common selection means.

Claim 6

The apparatus of claim 1 wherein there is further provided an erase means having first and second terminating regions and a control region therein by which said erase means is capable of being directed to effectively provide a conductive path of a selected conductivity between said erase means first and second terminating regions, said erase means first terminating region and said erase means control region both being electrically connected to a seventh terminal means adapted for electrical connection to a seventh selection means, and said erase means second terminating region being electrically connected to said tunneling capacitance means first polarity region.

Claim 7

The apparatus of claim 1 wherein there is further provided an erase means having first and second polarity regions partially electrically isolated from one another to prevent, at sufficiently small voltages therebetween, any significant electrical currents from traversing between said tunneling capacitance means first and second polarity regions but to permit significant electrical current to traverse between said tunneling capacitance means first and second polarity regions at larger voltages though these be voltages which are still sufficiently small to prevent electrical currents from traversing between said essentially variable threshold switching means control region and either of said first or second terminating regions of said essentially variable threshold switching means, said erase means first polarity region being electrically connected to a seventh terminal means adapted for electrical connection to a seventh selection means, and said erase means second polarity region being electrically connected to said essentially variable threshold switching means control region.

Claim 8

The apparatus of claim 2 wherein said second terminal means and said sixth terminal means are electrically interconnected and said second selection means and said sixth selection means are a common selection means.

Claim 9

The apparatus of claim 2 wherein said common selection means is capable of providing voltages of selected values to said first and fifth terminal means.

Claim 10

The apparatus of claim 3 wherein said common selection means is capable of providing voltages of selected values to said second and sixth terminal means.

Claim 11

The apparatus of claim 4 wherein said common selection means is capable of providing voltages of selected values to said fifth and sixth terminal means.

Claim 12

The apparatus of claim 7 wherein there is further provided an erase means having first and second terminating regions and a control region therein by which said erase means is capable of being directed to effectively provide a conductive path of a selected conductivity between said erase means first and second terminating regions, said erase means first terminating region and said erase means control region both being electrically connected to a seventh terminal means adapted for electrical connection to a seventh selection means, and said erase means second terminating region being electrically connected to said tunneling capacitance means first polarity region.

Claim 13

The apparatus of claim 7 wherein there is further provided an erase means having first and second polarity regions partially electrically isolated from one another to prevent, at sufficiently small voltages therebetween, any significant electrical currents from traversing between said tunneling capacitance means first and second polarity regions but to permit electrical current to traverse between said tunneling capacitance means first and second polarity regions at larger voltages though these be voltages which are still sufficiently small to prevent electrical currents from traversing between said essentially variable threshold switching means control region and either of said first or second terminating regions of said essentially variable threshold switching means, said erase means first polarity region being electrically connected to a seventh terminal means adapted for electrical connection to a seventh selection means, and said erase means second polarity region being electrically connected to said essentially variable threshold switching means control region.

Claim 14

The apparatus of claim 11 wherein that selection means common to said first and fifth selection means is capable of providing voltages of selected values at said first and fifth terminal means, that selection means common to said second and sixth selection means is capable of providing voltage of selected values at said second and sixth terminal means, said third selection means being capable of selecting for further use significant signals occurring on said third terminal means, said fourth selection means is capable of providing voltages of selected values on said fourth terminal means, and said seventh selection means is capable of providing voltages of selected values on said seventh terminal means.

Claim 15

The apparatus of claim 13 wherein said fixed threshold switching means, said control switching means and said erase means are enhancement mode, insulated gate field-effect transistors, and said essentially variable threshold switching means is an insulated gate field-effect transistor.

Claim 16

A non-volatile memory cell device, said device comprising: a semiconductor body of a first conductivity type in at least a first portion thereof, except in selected regions in said first body portion including first, second, third, fourth, fifth, sixth, seventh, eighth and ninth selected regions, said semiconductor material body having a first major surface wherein said first body portion intersects said major surface to form a first major surface portion; a series combination of a select insulated gate field-effect transistor and of a memory insulated gate field-effect transistor each having a pair of terminating regions therein serving as a source and drain thereof and each having at least one gate region therein, said select insulated gate field-effect transistor first terminating region being said first selected region which intersects said first major surface portion and which is electrically connected to a first terminal means adapted for electrical connection to a first selection means, said select insulated gate field-effect transistor gate being electrically connected to a second terminal means adapted for electrical connection to a second selection means, said select insulated gate field-effect transistor second terminating region being said second selected region which intersects said first major surface portion, said memory insulated gate field-effect transistor first terminating region being said third selected region which intersects said first major surface portion and which is electrically connected to said select insulated gate field-effect transistor second terminating region, said memory insulated gate field-effect transistor gate being a first extended conductor electrically isolated, at least everywhere except at a first tunneling region thereof, from other conductive portions of said cell at sufficiently small voltages therebetween to prevent any significant electrical currents from traversing therebetween, and said memory insulated gate field-effect transistor second terminating region being said fourth selected region which intersects said first major surface portion and which is electrically connected to a third terminal means adapted for electrical connection to a third selection means; a tunneling capacitance formed by said fifth selected region where said fifth selected region intersects said first major surface portion and by adjacent said tunneling region of said first extended conductor with said fifth selected region and said first extended conductor being separated by a first insulating layer sufficiently thin to permit significant electron tunneling currents to traverse between said fifth selected region and said first extended gate conductor at sufficiently large voltages but at voltages which are also sufficiently small so as to maintain that electrical isolation otherwise characterizing said first extended conductor as aforesaid, said fifth selected region being electrically isolated from said first, second, third and fourth selected regions to prevent any currents from traversing between said fifth selected region and any of said first, second, third or fourth selected regions at sufficiently small voltages therebetween; a coupling capacitance formed by said first extended conductor and a second extended conductor paralleling at least a substantial portion of said first extended conductor and separated therefrom by a second insulating layer, said second extended conductor being electrically connected to a fourth terminal means adapted for electrical connection to a fourth selection means; and a control insulated gate field-effect transistor having a pair of terminating regions therein serving as a source and drain thereof and having a gate therein, said control insulated gate field-effect transistor first terminating region being said sixth selected region which intersects said first major surface portion and which is electrically connected to a fifth terminal means adapted for electrical connection to a fifth selection means, said control insulated gate field-effect transistor gate being electrically connected to sixth terminal means adapted for electrical connection to a sixth selection means, and said control insulated gate field-effect transistor second terminating region being said seventh selected region which intersects said first major surface portion and which is electrically connected to said fifth selected region.

Claim 17

A non-volatile memory cell device, said device comprising: a semiconductor body of a first conductivity type in at least a first portion thereof, except in selected regions in said first body portion including first, second, third, fourth, fifth, sixth, seventh, eighth and ninth selected regions, said semiconductor material body having a first major surface wherein said first body portion intersects said major surface to form a first major surface portion; a series combination of a select insulated gate field-effect transistor and of a memory insulated gate field-effect transistor each having a pair of terminating regions therein serving as a source and drain thereof and each having at least one gate region therein, said select insulated gate field-effect transistor first terminating region being said first selected region which intersects said first major surface portion and which is electrically connected to a first terminal means adapted for electrical connection to a first selection means, said select insulated gate field-effect transistor gate being electrically connected to a second terminal means adapted for electrical connection to a second selection means, said select insulated gate field-effect transistor second terminating region being said second selected region which intersects said first major surface portion, said memory insulated gate field-effect transistor first terminating region being said third selected region which intersects said first major surface portion and which is electrically connected to said select insulated gate field-effect transistor second terminating region, said memory insulated gate field-effect transistor gate being a first extended conductor electrically isolated, at least everywhere except at a first tunneling region thereof, from other conductive portions of said cell at sufficiently small voltages therebetween to prevent any significant electrical currents from traversing therebetween, and said memory insulated gate field-effect transistor second terminating region being said fourth selected region which intersects said first major surface portion and which is electrically connected to a third terminal means adapted for electrical connection to a third selection means; a tunneling capacitance formed by said fifth selected region where said fifth selected region intersects said first major surface portion and by adjacent said tunneling region of said first extended conductor with said fifth selected region and said first extended conductor being separated by a first insulating layer sufficiently thin to permit significant electron tunneling currents to traverse between said fifth selected region and said first extended gate conductor at sufficiently large voltages but at voltages which are also sufficiently small so as to maintain that electrical isolation otherwise characterizing said first extended conductor as aforesaid, said fifth selected region being electrically isolated from said first, second, third and fourth selected regions to prevent any currents from traversing between said fifth selected region and any of said first, second, third or fourth selected regions at sufficiently small voltages therebetween; a coupling capacitance formed by said first extended conductor and a second extended conductor paralleling at least a substantial portion of said first extended conductor and separated therefrom by a second insulating layer, said second extended conductor being electrically connected to a fourth terminal means adapted for electrical connection to a fourth selection means; and a control insulated gate field-effect transistor having a pair of terminating regions therein serving as a source and drain thereof and having a gate therein, said control insulated gate field-effect transistor first terminating region being said sixth selected region which intersects said first major surface portion and which is electrically connected to a fifth terminal means adapted for electrical connection to a fifth selection means, said control insulated gate field-effect transistor gate being electrically connected to sixth terminal means adapted for electrical connection to a sixth selection means, and said control insulated gate field-effect transistor second terminating region being said seventh selected region which intersects said first major surface portion and which is electrically connected to said fifth selected region.

Claim 18

The apparatus of claim 15 wherein said first terminal means and said fifth terminal means are electrically interconnected and said first selection means and said fifth selection means are a common selection means.

Claim 19

The apparatus of claim 15 wherein said second terminal means and said sixth terminal means are electrically interconnected and said second selection means and said sixth selection means are a common selection means.

Claim 20

The apparatus of claim 15 wherein said fifth terminal means and said sixth terminal means are electrically interconnected and said fifth selection and said sixth selection means are a common selection means.

Claim 21

The apparatus of claim 15 wherein there is further provided an erase insulated gate field-effect transistor having a pair of terminating regions therein serving as a source and drain thereof and having a gate therein, said erase insulated gate field-effect transistor first terminating region, serving as said eighth selected region and which intersects said first major surface portion, and said erase insulated gate field-effect transistor gate together being electrically connected to a seventh terminal means adapted for electrical connection to a seventh selection means, and said erase insulated gate field-effect transistor second terminating region being said ninth selected region which intersects said first major portion and which is electrically connected to said fifth selected region.

Claim 22

The apparatus of claim 13 wherein there is further provided an erase tunneling capacitance formed by said eighth selected region where said eighth selected region intersects said first major surface portion and by an adjacent second tunneling region of said first extended conductor with said first eighth selected region and said first extended conductor being separated by a first insulating layer sufficiently thin to permit significant electron tunneling currents to traverse between said eighth selection region and said first extended gate conductor at sufficiently large voltages but at voltages which are also sufficiently small so as to maintain that electrical isolation effectively otherwise characterizing said first extended conductor as aforesaid, said eighth selected region being electrically connected to a seventh terminal means adapted for electrical connection to a seventh selection means.

Claim 23

The apparatus of claim 15 wherein said second and third selected regions are a single common region, and said fifth and seventh selected regions are a single common region.

Claim 24

The apparatus of claim 16 wherein said second terminal means and said sixth terminal means are electrically interconnected and said second selection means and said sixth selection means are a common selection means.

Claim 25

The apparatus of claim 16 wherein said common selection means is capable of providing voltages of selected values to said first and fifth terminal means.

Claim 26

The apparatus of claim 16 wherein said first and sixth selected regions are a single common region.

Claim 27

The apparatus of claim 17 wherein said common selection means is capable of providing voltages of selected values to said second and sixth terminal means.

Claim 28

The apparatus of claim 17 wherein said select insulated gate field-effect transistor gate and said control insulated gate field-effect transistor gate are formed in common by a third extended conductor.

Claim 29

The apparatus of claim 18 wherein said common selection means is capable of providing voltages of selected values to said fifth and sixth terminal means.

Claim 30

The apparatus of claim 22 wherein there is further provided an erase insulated gate field-effect transistor having a pair of terminating regions therein serving as a source and drain thereof and having a gate therein, said erase insulated gate field-effect transistor first terminating region, serving as said eighth selected region and which intersects said first major surface portion, and said erase insulated gate field-effect transistor gate together being electrically connected to a seventh terminal means adapted for electrical connection to a seventh selection means, and said erase insulated gate field-effect transistor second terminating region being said ninth selected region intersecting said first major portion and which is electrically connected to said fifth selected region.

Claim 31

The apparatus of claim 22 wherein there is further provided an erase tunneling capacitance formed by said eighth selected region where said eighth selected region intersects said first major surface portion and by an adjacent second tunneling region of said first extended conductor with said eighth selected region and said first extended conductor being separated by a first insulating layer sufficiently thin to permit electron tunneling currents to traverse between said eighth selection region and said first extended gate conductor at sufficiently large voltages but at voltages which are also sufficiently small so as to maintain that electrical isolation effectively otherwise characterizing said first extended conductor as aforesaid, said eight selected region being electrically connected to a seventh terminal means adapted for electrical connection to a seventh selection means.

Claim 32

The apparatus of claim 22 wherein said first and sixth selected regions are a single common region, said second and third selected regions are a single common region, said fifth and seventh selected regions are a single common region, and said select insulated gate field-effect transistor gate and said control insulated gate field-effect transistor gate are formed in common by a third extended conductor.

Claim 33

The apparatus of claim 28 wherein that selection means common to said first and fifth selection means is capable of providing voltages of selected values at said first and fifth terminal means, that selection means common to said second and sixth selection means is capable of providing voltage of selected values at said second and sixth terminal means, said third selection means being capable of selecting for further use significant signals occurring on said third terminal means, said fourth selection means is capable of providing voltages of selected values on said fourth terminal means, and said seventh selection means is capable of providing voltages of selected values on said seventh terminal means.

Claim 34

The apparatus of claim 28 wherein said first and sixth selected regions are a single common region, said second and third selected regions are a single common region, and fifth, seventh and ninth selected regions are a single common region, and said select insulated gate field-effect transistor gate and said control insulated gate field-effect transistor gate are formed in common by a third extended conductor.

Claim 35

The apparatus of claim 31 wherein said select insulated gate field-effect transistor, said control insulated gate field-effect transistor and said erase insulated gate field-effect transistor are enhancement mode transistors.

Claim 36

The apparatus of claim 32 wherein said select insulated gate field-effect transistor, said control insulated gate field-effect transistor and said erase insulated gate field-effect transistor are enhancement mode transistors.