US4459683A
Expired / Lapsed
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Read resettable memory circuit
Assignee: Signetics Corp
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Filing: 1982-04-14
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Granted: 1984-07-10
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Expires: 2002-04-14
Abstract
Abstract A read resettable memory circuit contains a flip-flop circuit (10) consisting of a flip-flop (FF) and an edge-triggered control circuit (CC) and a fall-through latch (16). The control circuit sets the flip-flop in response to a selected edge transition in a first clock (.0. 1 ) when an appropriate external logical set signal (S) is received and resets the flip-flop in response to a selected edge transition in a second clock (.0. 2 ) when an appropriate feedback logical reset signal (R) is received. The latch provides the reset signal at a value corresponding to the current logic state of the flip-flop during each period running from the selected edge transition of the second clock to its opposite edge transition and at a value corresponding to the logic state of the flip-flop that exists just before each opposite edge transition of the second clock during each remaining following period.
Inventors
- 👤 Singh B. Yalamanchili
- 👤 Syed T. Mahmud
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 16:22
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356017; H03K3/356052; H03K3/35606
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
273 words
A memory circuit which contains a flip-flop and is controlled by a first clocking signal that repetitively makes a pair of first transitions of which one goes from a first low level up to a first high level and the other goes from the first high level down to the first low level and by a second clocking signal that repetitively makes a pair of second transitions of which one goes from a second low level up to a second high level and the other goes from the second high level down to the second low level, characterized by: edge-triggered control means responsive to the occurrence of a selected one of the pair of first transitions for setting the flip-flop to a first logic state when a logical set signal supplied thereto is at a first logical value corresponding to the first logic state and responsive to the occurrence of a selected one of the pair of second transitions for resetting the flip-flop to a second logic state opposite to the first logic state when a logical reset signal supplied thereto is at the first logical value; and latch means for providing the reset signal at a logical value which corresponds to the logic state of the flip-flop substantially while the second clocking signal is at the particular second level that occurs just after the selected second transition and which corresponds to the logic state of the flip-flop that existed just before the second clocking signal made the second transition opposite to the selected second transition substantially while the second clocking signal is at the second level opposite to the particular second level.
Claim 2
Dependent Claim
273 words
A memory circuit which contains a flip-flop and is controlled by a first clocking signal that repetitively makes a pair of first transitions of which one goes from a first low level up to a first high level and the other goes from the first high level down to the first low level and by a second clocking signal that repetitively makes a pair of second transitions of which one goes from a second low level up to a second high level and the other goes from the second high level down to the second low level, characterized by: edge-triggered control means responsive to the occurrence of a selected one of the pair of first transitions for setting the flip-flop to a first logic state when a logical set signal supplied thereto is at a first logical value corresponding to the first logic state and responsive to the occurrence of a selected one of the pair of second transitions for resetting the flip-flop to a second logic state opposite to the first logic state when a logical reset signal supplied thereto is at the first logical value; and latch means for providing the reset signal at a logical value which corresponds to the logic state of the flip-flop substantially while the second clocking signal is at the particular second level that occurs just after the selected second transition and which corresponds to the logic state of the flip-flop that existed just before the second clocking signal made the second transition opposite to the selected second transition substantially while the second clocking signal is at the second level opposite to the particular second level.
Claim 3
Dependent Claim
149 words
A memory circuit as in claim 1 wherein the selected first transition is the beginning of a write period that extends to the next first transition opposite to the selected first transition and wherein the opposite second transition is substantially the beginning of a read period that extends substantially to the next selected second transition, characterized in that, in the situation where a first one of the read periods occurs and then a second one of the read periods occurs separated from the first read period by only a first one of the write periods that is completed before the second read period where the set signal is at the first logical value when the first write period begins, the flip-flop is set at the first logic state which is saved for the second read period provided that the first read period is completed before the first write period.
Claim 4
Dependent Claim
41 words
A memory circuit as in claim 2 characterized in that the first logic state is saved for the second read period even though the set signal is at the first logical value during at least part of the first read period.
Claim 5
Dependent Claim
122 words
A memory circuit as in claim 1 characterized in that the control means comprises: a set trigger for setting the flip-flop to the first logic state; a reset trigger for resetting the flip-flop to the second logic state; and inhibiting means for inhibiting the set trigger selectively while the first clocking signal is at the particular first level that occurs just after each selected first transition in response to which the set trigger set the flip-flop to the first logic state and for inhibiting the reset trigger selectively while the second clocking signal is at the particular second level that occurs just after each selected second transition in response to which the reset trigger reset the flip-flop to the second logic state.
Claim 6
Dependent Claim
51 words
A memory circuit as in claim 4 characterized in that, after the set trigger sets the flip-flop to the first logic state, the inhibiting means inhibits the set trigger during the entire period that the first clocking signal is at the particular first level that follows the setting of the flip-flop.
Claim 7
Dependent Claim
49 words
A memory circuit as in claim 5 characterized in that the inhibiting means inhibits the reset trigger only while the first clocking signal is also at the particular first level provided further that the set signal was at the first logical value just prior to the selected first transition.
Claim 8
Dependent Claim
126 words
A memory circuit as in claim 4 wherein the flip-flop is controlled through a first node from which a first logical flip-flop signal indicative of the logic state of the flip-flop is taken and through a second node from which a second logical flip-flop signal complementary to the first flip-flop signal is taken, characterized in that the inhibiting means comprises: a first field-effect transistor (FET) whose source is coupled to a substantially constant voltage supply, whose gate electrode is coupled to the first node, and whose drain is coupled to the set trigger; and a second FET whose source is coupled to the voltage supply, whose gate electrode is coupled to the drain of the first FET, and whose drain is coupled to the reset trigger.
Claim 9
Dependent Claim
46 words
A memory circuit as in claim 7 characterized in that the inhibiting means further includes a third FET whose source and drain are coupled between the voltage supply and the source of the second FET and whose gate electrode is responsive to the first clocking signal.
References Cited (Backward Citations)
US4224533A
Cited
US4379241A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-07-10 | 1988-01-09 | 1988-07-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-07-10 | 1992-01-09 | 1992-07-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-07-10 | 1996-01-09 | 1996-07-10 | $7700.00 | Window Closed / Lapsed |