Control of page storage among three media using a single channel processor program and a page transfer bus

Claim 2

Digital error correcting circuitry, for correcting signals for offset errors, comprising: means for providing the signals in digital form and which signals have a first phase relationship when a first signal leads a second signal identifying a first direction, and a second phase relationship when the first signal lags the second signal identifying a second direction; detection means for detecting the peak amplitude values of each of the signals; storage means for storing the detected peak amplitude values of each of the signals, in response to a storage command signal and which may store such peak amplitude values for an indefinite time period, which may substantially exceed the time required for correction of signals for offset errors; bias determining means responsive to the stored peak amplitude values, including the last of the stored peak amplitude values and which may have been stored for a substantial period of time, for providing a bias signal for each of the signals to be corrected, each bias signal having a magnitude and polarity equal to the offset from a zero baseline of a respective one of the signals to be corrected; and offset correction means responsive to the bias signal and to the signals to be corrected, for applying the bias signals to the signals to be corrected in such manner to be additive to or subtractive from the signals to be corrected, whereby the offset errors are cancelled by the bias signals.

Claim 3

Digital error correcting circuitry for correcting first and second signals for amplitude errors, comprising: means for providing the first and second signals in digital form; detection means for detecting the peak amplitude values of the first and second signals; storage means for storing the detected peak amplitude values of the first and second signals, in response to a storage command signal; and amplitude correction means, responsive to the stored peak amplitude values of the first and second signals for determining the ratio of the peak-to-peak amplitude of the first signal to the peak-to-peak amplitude of the second signal and for providing an amplitude correction factor, said amplitude correciton factor being applied to at least one of the first and second signals in such manner to raise or lower the amplitude of one of the first or second signals relative to the other so that the peak-to-peak amplitude of the second signal is made equal to the peak-to-peak amplitude of the first signal.

Claim 4

Digital error correcting circuitry for correcting first and second signals for amplitude errors, comprising: means for providing the first and second signals in digital form; detection means for detecting the peak amplitude values of the first and second signals; storage means for storing the detected peak amplitude values of the first and second signals, in response to a storage command signal; and amplitude correction means, responsive to the stored peak amplitude values of the first and second signals for determining the ratio of the peak-to-peak amplitude of the first signal to the peak-to-peak amplitude of the second signal and for providing an amplitude correction factor, said amplitude correciton factor being applied to at least one of the first and second signals in such manner to raise or lower the amplitude of one of the first or second signals relative to the other so that the peak-to-peak amplitude of the second signal is made equal to the peak-to-peak amplitude of the first signal.

Claim 5

Digital error correcting circuitry for correcting first and second signals for offset and amplitude errors, comprising: means for providing the first and second signals in digital form; detection means for detecting the peak amplitude values of the first and second signals; storage means for storing the detected peak amplitude values of the first and second signals, in response to a storage command signal; bias determining means responsive to the stored peak amplitude values for providing first and second bias signals, each having a magnitude and polarity equal to the offset from a zero baseline of a repective one of the first and second signals; offset correction means responsive to the first and second bias signals and to the first and second signals for applying the first and second bias signals to the first and second signals, respectively, whereby the offset errors of the first and second signals are cancelled by the first and second bias signals, respectively, providing first and second offset corrected signals; and amplitude correction means responsive to the stored peak amplitude values of the first and second signals and to the second offset corrected signal for determining the ratio of the peak-to-peak amplitude of the first signal to the peak-to-peak amplitude of the second signal and for providing an amplitude correction factor, said amplitude correction factor being applied to at least one of the first and second signals to raise or lower the amplitude of one of the signals relative to the other so that the peak-to-peak amplitude of the second offset corrected signal is made equal to the peak-to-peak amplitude of the first offset corrected signal.

Claim 6

Digital error correcting circuitry for correcting first and second signals for offset and amplitude errors, comprising: means for providing the first and second signals in digital form; detection means for detecting the peak amplitude values of the first and second signals; storage means for storing the detected peak amplitude values of the first and second signals, in response to a storage command signal; bias determining means responsive to the stored peak amplitude values for providing first and second bias signals, each having a magnitude and polarity equal to the offset from a zero baseline of a repective one of the first and second signals; offset correction means responsive to the first and second bias signals and to the first and second signals for applying the first and second bias signals to the first and second signals, respectively, whereby the offset errors of the first and second signals are cancelled by the first and second bias signals, respectively, providing first and second offset corrected signals; and amplitude correction means responsive to the stored peak amplitude values of the first and second signals and to the second offset corrected signal for determining the ratio of the peak-to-peak amplitude of the first signal to the peak-to-peak amplitude of the second signal and for providing an amplitude correction factor, said amplitude correction factor being applied to at least one of the first and second signals to raise or lower the amplitude of one of the signals relative to the other so that the peak-to-peak amplitude of the second offset corrected signal is made equal to the peak-to-peak amplitude of the first offset corrected signal.

Claim 7

The digital error correcting circuitry of either of claims 2 or 3 in which the means for providing the signals in digital form includes analog to digital conversion means.

Claim 8

The digital error correcting circuitry of either of claims 2 or 3 in which the storage means includes a digital storage register whose contents are revised in response to the storage command signal.

Claim 9

The digital error correcting circuitry of claim 5 in which the storage command signal is provided each time the circuitry is furnished with operating power.

Claim 10

The digital error correcting circuitry of claim 3 in which the bias determining means includes means for determining one-half the sum of the positive peak amplitude and negative peak amplitude of each signal to be corrected.

Claim 11

The digital correcting circuitry of claim 3 in which the offset correction means includes means for subtracting the bias signals from the signals to be corrected.

Claim 22

Digital error correcting circuitry, for correcting signals for offset errors, comprising: means for providing the signals in digital form; detection means for detecting the peak amplitude values of each of the signals; storage means for storing the detected peak amplitude values of each of the signals, in response to a storage command signal; bias determining means responsive to the stored peak amplitude values, for providing a bias signal for each of the signals to be corrected, each bias signal having a magnitude and polarity equal to the offset from a zero baseline of a respective one of the signals to be corrected; amplitude correction means responsive to the stored peak amplitude values of the first and second signals and providing an amplitde corrected signal; offset correction means responsive to the bias signals and to the signals to be corrected, for applying the bias signals to the signals to be corrected, in such manner to be additive to or subtractive from the signals to be corrected, whereby the offset errors are cancelled by the bias signals to provide offset corrected signals; and means for receiving the offset corrected signals and amplitude corrected signal for providing a combined corrected signal.

Claim 23

Digital error correcting circuitry, for correcting signals for offset errors, comprising: means for providing the signals in digital form; detection means for detecting the peak amplitude values of each of the signals; storage means for storing the detected peak amplitude values of each of the signals, in response to a storage command signal; bias determining means responsive to the stored peak amplitude values, for providing a bias signal for each of the signals to be corrected, each bias signal having a magnitude and polarity equal to the offset from a zero baseline of a respective one of the signals to be corrected; amplitude correction means responsive to the stored peak amplitude values of the first and second signals and providing an amplitde corrected signal; offset correction means responsive to the bias signals and to the signals to be corrected, for applying the bias signals to the signals to be corrected, in such manner to be additive to or subtractive from the signals to be corrected, whereby the offset errors are cancelled by the bias signals to provide offset corrected signals; and means for receiving the offset corrected signals and amplitude corrected signal for providing a combined corrected signal.

Claim 24

The digital error correcting circuitry of claim 18 in which the bias determining means includes means for determining one-half the sum of the positive peak amplitude and negative peak amplitude of each signal to be corrected.

Claim 25

The digital error correcting circuitry of claim 16 in which the offset correction means includes means for subtracting the bias signals from the signals to be corrected.

Claim 26

Digital error correcting circuitry for correcting first and second signals for amplitude errors, comprising: means for providing the first and second signals in digital form and which signals have a first phase relationship when the first signal leads the second signal identifying a first direction, and a second phase relationship when the first signal lags the second signal identifying a second direction; detection means for detecting the peak amplitude values of the first and second signals; storage means for storing the detected peak amplitude values of the first and second signals, in response to a storage command signal and which stores said peak amplitude values for an indefinite period of time; and amplitude correction means, responsive to the stored peak amplitude values, including the last of the stored peak amplitude values, of the first and second signals and to the second signal, for providing an amplitude correction factor, said amplitude correction factor being applied to at least one of said first or second signals in such manner to raise or lower the amplitude of one of the first or second signals relative to the other so that the peak-to-peak amplitude of the second signal is made equal to the peak-to-peak amplitude of the first signal.

Claim 27

Digital error correcting circuitry for correcting first and second signals for amplitude errors, comprising: means for providing the first and second signals in digital form and which signals have a first phase relationship when the first signal leads the second signal identifying a first direction, and a second phase relationship when the first signal lags the second signal identifying a second direction; detection means for detecting the peak amplitude values of the first and second signals; storage means for storing the detected peak amplitude values of the first and second signals, in response to a storage command signal and which stores said peak amplitude values for an indefinite period of time; and amplitude correction means, responsive to the stored peak amplitude values, including the last of the stored peak amplitude values, of the first and second signals and to the second signal, for providing an amplitude correction factor, said amplitude correction factor being applied to at least one of said first or second signals in such manner to raise or lower the amplitude of one of the first or second signals relative to the other so that the peak-to-peak amplitude of the second signal is made equal to the peak-to-peak amplitude of the first signal.

Claim 28

The digital error correcting circuitry of claim 19 in which the amplitude correction means includes means for determining the ratio of the peak-to-peak amplitude of the first signal to the peak-to-peak amplitude of the second signal.

Claim 31

The method of claim 21 in which the step of providing the signals in digital form includes the step of converting the signals from analog to digital form.

Claim 32

The method of claim 21 in which the step of storing the detected peak amplitude values in response to a storage command signal includes the step of providing the storage command signal each time operating power is furnished.

Claim 33

The method of claim 21 in which the step of providing bias signals includes the step of determining one half the sum of the positive peak amplitude and the negative peak amplitude of each signal to be corrected.

Claim 34

The method of claim 21 in which the step of applying bias signals to the signals to be corrected includes the step of subtracting the bias signals from the signals to be corrected.

Claim 37

The method of claim 26 in which the step of providing an amplitude correction factor includes the step of determining the ratio of the peak-to-peak amplitude of the first signal to the peak-to-peak amplitude of the second signal.