US4456929A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Solid state image pick-up apparatus
Assignee: Hitachi Ltd
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Filing: 1982-06-04
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Granted: 1984-06-26
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Expires: 2002-06-04
Abstract
Abstract In a solid state image pick-up device of the type comprising a first semiconductor layer including a photoelectric conversion element array, and vertical and horizontal switching elements adapted to select the photoelectric conversion elements, a second semiconductor layer including a horizontal shift register for selecting the horizontal switching elements, a third semiconductor layer including a vertical shift register for selecting the vertical switching elements, the first, second and third semiconductor layers are insulated from each other, and gate voltage V SMOS .L impressed upon a gate electrode of a not selected horizontal switching element is made to satisfy a relation V SMOS .L ≧V WPD +F FB where V WPD represents a potential of the first semiconductor layer, and V FB a flat band voltage beneath gate electrodes of the horizontal switching elements.
Inventors
- 👤 Masakazu Aoki
- 👤 Haruhisa Ando
- 👤 Shinya Ohba
- 👤 Iwao Takemoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 23:04
CPC Classifications
H; H04; H04N; H04N25/00; H04N25/60; H04N25/67; H04N25/671; H04N25/677; H04N25/70; H04N25/76; H04N25/78
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
126 words
Solid state image pick-up apparatus comprising: a first semiconductor layer including a photoelectric conversion element array, and vertical and horizontal switching elements adapted to select said photoelectric conversion elements; a second semiconductor layer including a horizontal shift register for selecting said horizontal switching elements; a third semiconductor layer including a vertical shift register for selecting said vertical switching elements; said first, second and third semiconductor layers being electricaly insulated from each other; and means for causing gate voltage V SMOS .L impressed upon a gate electrode of a not selected horizontal switching element to satisfy a relation V.sub.SMOS.L ≧V.sub.WPD +V.sub.FB where V WPD represents a potential of said first semiconductor layer, and V FB a flat band voltage beneath gate electrodes of said horizontal switching elements.
Claim 2
Dependent Claim
126 words
Solid state image pick-up apparatus comprising: a first semiconductor layer including a photoelectric conversion element array, and vertical and horizontal switching elements adapted to select said photoelectric conversion elements; a second semiconductor layer including a horizontal shift register for selecting said horizontal switching elements; a third semiconductor layer including a vertical shift register for selecting said vertical switching elements; said first, second and third semiconductor layers being electricaly insulated from each other; and means for causing gate voltage V SMOS .L impressed upon a gate electrode of a not selected horizontal switching element to satisfy a relation V.sub.SMOS.L ≧V.sub.WPD +V.sub.FB where V WPD represents a potential of said first semiconductor layer, and V FB a flat band voltage beneath gate electrodes of said horizontal switching elements.
Claim 3
Dependent Claim
39 words
The apparatus according to claim 1 wherein said gate voltage V SMOS .L satisfies the following relation V.sub.SMOS.L <V.sub.V +V.sub.SMOS.T where V SMOS .T represents a threshold voltage of the horizontal switching elements, and V V a video voltage.
Claim 4
Dependent Claim
23 words
The apparatus according to claim 1 or 2 wherein each of said horizontal switching elements comprises an insulated gate type field effect transistor.
Claim 5
Dependent Claim
34 words
The apparatus according to claim 3 wherein a bias voltage is impressed upon said first semiconductor layer so as to accumulate electric charge beneath a gate electrode of a not selected vertical switching element.
Claim 6
Dependent Claim
24 words
The apparatus according to claim 1 wherein said first, second and third semiconductor layers respectively comprise well diffusion region formed on a semiconductor substrate.
Claim 7
Dependent Claim
78 words
The apparatus according to claim 1 which further comprises a circuit for producing pulses utilized to drive said horizontal shift register, said circuit comprises a P and N channel MOS field effect transistors which are connected as a complement type inverter, means for applying a timing pulse to gate electrodes of said MOS field effect transistors, and a diode connected to a source electrode of one of said MOS field effect transistors to obtain a low level voltage.
References Cited (Backward Citations)
US4360833A
Cited
US4407010A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-06-26 | 1987-12-26 | 1988-06-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-06-26 | 1991-12-26 | 1992-06-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-06-26 | 1995-12-26 | 1996-06-26 | $7700.00 | Window Closed / Lapsed |