Digital circuit for providing a binary signal on the occurrence of a predetermined frequency ratio of two signals

Claim 1

A digital circuit for providing a binary signal on the occurrence of a predetermined frequency ratio between the frequencies of a first and a second signal during a suitable measuring period, comprising: an up-counter having a capacity greater than the predetermined frequency ratio, said up-counter having a count input, an output for a first count that is slightly lower than a second count corresponding to the predetermined frequency ratio, the higher frequency first signal being applied to the count input; a monostable multivibrator having a trigger input, a dwell time equal to twice the period required by the up-counter to count from the first count to the second count output, said trigger input connected to the first count output of the up-counter; an up-down counter having a control input being connected to the output of the monostable multivibrator, a count input provided with the second signal, the zero state and maximum count being locked up and a count output corresponding to about one-fifth of the maximum count; a memory having a control input and a data input, said data input being connected to the output of the updown counter, said control input being such that when it receives a pulse, it causes an L level signal appearing at the data input to be written into the memory and to be read at the end of said pulse and then erased; means for providing pulses to the control input in response to one of two signals including the second signal and signals synchronous with the vertical deflection of a television receiver; a measuring period determining counter whose maximum count is locked up having a count input, an enable input, a maximum count output and a reset input, the count input being connected to the output of the means for providing pulses, the enable input being connected to the output of the memory, the maximum count output providing the output of the digital circuit; inverter means for receiving the count output of the up-down counter and for providing a signal inversely corresponding thereto, said signal being provided to the reset input of the measuring period determining counter; a NOR gate having a first input connected to the output of said memory and a second input connected to the output of the digital circuit and an output; and an AND gate having a first input connected to the output of the NOR gate and a second input receiving the second signal and having an output connected to the reset input of the up-counter.