Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
226 words
A light emission delay circuit for a timing light for adjusting the emission of light resulting from an ignition signal to a time when a piston in an engine cylinder reaches a top dead center position, comprising: (a) first means responsive to a first signal indicative of the time for the ignition of a particular engine cylinder and a second signal having a leading edge substantially indicating the ignition time of each engine cylinder for producing a third signal having a leading edge aligned with a leading edge of said second signal, said third signal being substantially two periods of said second signal beyond said first signal and having a pulse width equal to the period of said second signal; (b) second means for delaying said leading edge of said third signal; (c) third means for generating a fourth signal having a leading edge aligned with the leading edge of said third signal as delayed by said second means and a trailing edge aligned with a trailing edge of said third signal as supplied from said first means; and (d) fourth means for counting a clock signal upwardly during the interval of said forth signal and then counting said clock signal downwardly during an interval equal to said interval of said fourth signal to produce an output signal for enabling the timing light to emit light.
Claim 2
Dependent Claim
226 words
A light emission delay circuit for a timing light for adjusting the emission of light resulting from an ignition signal to a time when a piston in an engine cylinder reaches a top dead center position, comprising: (a) first means responsive to a first signal indicative of the time for the ignition of a particular engine cylinder and a second signal having a leading edge substantially indicating the ignition time of each engine cylinder for producing a third signal having a leading edge aligned with a leading edge of said second signal, said third signal being substantially two periods of said second signal beyond said first signal and having a pulse width equal to the period of said second signal; (b) second means for delaying said leading edge of said third signal; (c) third means for generating a fourth signal having a leading edge aligned with the leading edge of said third signal as delayed by said second means and a trailing edge aligned with a trailing edge of said third signal as supplied from said first means; and (d) fourth means for counting a clock signal upwardly during the interval of said forth signal and then counting said clock signal downwardly during an interval equal to said interval of said fourth signal to produce an output signal for enabling the timing light to emit light.
Claim 3
Dependent Claim
46 words
A light emission delay circuit according to claim 1, including means for producing a signal indicative of one out of a plurality of engine cylinders, said first means being responsive to said last-mentioned signal for generating said third signal for said one of the engine cylinders.
Claim 4
Dependent Claim
85 words
A light emission delay circuit according to claim 1, wherein said second means comprises a timer circuit connected to an output terminal of said first means and having an output terminal, an inverter having an input terminal connected to said output terminal of said timer circuit and an output, and an AND gate having a first input terminal connected to said first means, a second input terminal connected to said output terminal of said inverter, and an output for delivering said third signal as delayed.
Claim 5
Dependent Claim
113 words
A light emission delay circuit according to claim 1, wherein said third means comprises a clock input terminal for supplying said clock signal, an inverter having an input terminal connected to an output terminal of said second means, a first AND gate having a first input terminal connected to said output terminal of said second means, a second input terminal connected to said clock input terminal, and a first output connected to said fourth means, and a second AND gate having a first input terminal connected to said output terminal of said inverter, a second input terminal connected to said clock input terminal, and a second output terminal connected to said fourth means.
Claim 6
Dependent Claim
60 words
A light emission delay circuit according to claim 4, wherein said fourth means comprises an up-down counter having an up-count input terminal connected to said first output terminal of said first AND gate, a down-count input terminal connected to said second output terminal of said second AND gate, and an output for producing said output signal of said fourth means.