US4453228A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Component selection system for a multiple line adapter organization
Assignee: Unisys Corp
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Filing: 1982-03-30
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Granted: 1984-06-05
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Expires: 2002-03-30
Abstract
Abstract A multiple group of line adapters in a data-comm I/O subsystem is controlled by a microprocessor which provides for selection and control of components associated with each line adapter in the organization.
Inventors
- 👤 Richard A. Loskorn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 19:33
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/382; G06F13/385; G06F13/10; G06F13/12; G06F13/124
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
142 words
In a line support processor for controlling data transfer operations between a host computer and remote data terminals, wherein said line support processor includes a plurality of line adapters, a data link interface unit with local memory and a microprocessor, said microprocessor including program data in an internal ROM and external RAM storage means and having an I/O bus and output control registers providing control data and information data to said line adapters, a component selection system for a multiple line adapter organization comprising: (a) a plurality of line adapters, each of which includes its own line adapter memory and a data-comm line to a remote terminal, each of said line adapters being operatively controlled by said microprocessor; (b) logic means for decoding command signals from said microprocessor and conveying said signals to a specific line adapter in said line adapter organization.
Claim 2
Dependent Claim
142 words
In a line support processor for controlling data transfer operations between a host computer and remote data terminals, wherein said line support processor includes a plurality of line adapters, a data link interface unit with local memory and a microprocessor, said microprocessor including program data in an internal ROM and external RAM storage means and having an I/O bus and output control registers providing control data and information data to said line adapters, a component selection system for a multiple line adapter organization comprising: (a) a plurality of line adapters, each of which includes its own line adapter memory and a data-comm line to a remote terminal, each of said line adapters being operatively controlled by said microprocessor; (b) logic means for decoding command signals from said microprocessor and conveying said signals to a specific line adapter in said line adapter organization.
Claim 3
Dependent Claim
90 words
The selection system of claim 1, wherein said logic means includes: (a) a designate flip-flop for each separate line adapter; (b) comparator means in said data link interface unit, said comparator means including: (b1) a first set of input signals on address lines from said microprocessor; (b2) a second set of preset input signals; (b3) first and second output lines for signal output reflective of equality or non-equality between said first and second input signals to respectively select either said local data link interface memory or said line adapter memory.
Claim 4
Dependent Claim
30 words
The selection system of claim 2, which includes: (a) jumper connection means from each line of said I/O bus to a different designate flip-flop for uniquely identifying each designate flip-flop.
Claim 5
Dependent Claim
27 words
The selection means of claim 3, wherein each pair of line adapters includes its own: (a) multiplexor means for selecting data for transfer to said I/O bus.
Claim 6
Dependent Claim
23 words
The selection means of claim 3, which includes: (a) means to selectively designate a particular line adapter in said multiple line adapter organization.
Claim 7
Dependent Claim
50 words
The selection means of claim 5, wherein said means to selectively designate a line adapter includes: (a) a PUT operator instruction from said microprocessor which places a pointer bit (=1) on a single particular jumper line of said I/O bus and strobes said designate flip-flop to set said designate flip-flop.
Claim 8
Dependent Claim
46 words
The selection system of claim 6, wherein each of said line adapters further includes: (a) input/output circuit means connected to a remote terminal and to said host computer, via said multiplexor, for effectuating command signals from said microprocessor for handling data transfers with a specified protocol.
Claim 9
Dependent Claim
32 words
The selection system of claim 7, wherein each of said input/output circuit means uses components which include: (a) a protocol controller means; (b) a first program timer; (c) a second program timer.
Claim 10
Dependent Claim
24 words
The selection system of claim 8, which includes: (a) means to read which component of a designated line adapter requires service from said microprocessor.
Claim 11
Dependent Claim
63 words
The selection system of claim 9, wherein said means to read which component requests service includes: (a) means, by each component, to set (=1) a unique line on said I/O bus particular only to itself; (b) a GET operator from said microprocessor to read which component on said line adapter is set via said I/O bus, thus to identify the component requesting service.
Claim 12
Dependent Claim
22 words
The selection system of claim 4, which includes: (a) means to address a particular RAM memory storage means in a designated adapter.
Claim 13
Dependent Claim
33 words
The component selection system of claim 6, wherein said microprocessor includes first and second output control registers connected to said I/O bus, and each line adapter includes a USART chip and timer chip.
Claim 14
Dependent Claim
46 words
The system of claim 12, wherein said second output control register includes: (a) first and second dedicated bit positions which provide an output to said multiplexor, and settable by said microprocessor, to select either said USART chip or said timer chip in a designated line adapter.
References Cited (Backward Citations)
US4393461A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-06-05 | 1987-12-05 | 1988-06-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-06-05 | 1991-12-05 | 1992-06-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-06-05 | 1995-12-05 | 1996-06-05 | $7700.00 | Window Closed / Lapsed |