DC To AC power inverter

Claim 2

In a DC to AC power inverter of the class B,C,D, or E type which includes a battery, at least one power SCR and associated capacitor circuitry and at least one input winding on a main transformer core and which requires a quiescent current to establish operating current for capacitor commutation charge, the improvement comprising circuit means for feeding current generated by the quiescent current back to the battery; said circuit means including an isolated feedback winding on the main transformer core and rectifying means coupled directly between said feedback winding and the battery; and said feedback winding having a slightly higher number of turns than said input winding such that a voltage slightly higher than the battery voltage is generated across said feedback winding so that there is a current draw by the battery from said feedback winding sufficient to establish said quiescent current through the input winding for quiescent operation required for capacitor commutation charge.

Claim 3

The inverter of claim 1 wherein said rectifying means include a full wave diode rectifier bridge.

Claim 4

The inverter of claim 1 wherein said feedback winding has approximately 4% more turns than said input winding.

Claim 5

In a DC to AC power inverter of the class B,C,D or E type which includes a battery, at least one power SCR and associated capacitor circuitry, and at least one input winding on a main transformer core, which also has thereon at least one secondary output winding, the improvement comprising self-detecting load demand circuit means coupled to a line from said output winding for cyclically energizing the inverter, for sensing a minimum AC load across said secondary winding, and upon sensing a minimum AC load, for holding said inverter in an energized state until less than a minimum AC load is sensed during an energizing cycle; said load demand circuit means including a current transformer circuit having a primary winding comprised of at least one turn formed by a line from one end of the output secondary winding; and a multi-turn secondary winding, such that a load current flowing through said line generates a voltage across said secondary winding; means for cyclically energizing said inverter; means for sensing a load current flowing in the output secondary winding; and, means for holding said inverter in an energized state when and while a minimum load current is flowing through the output secondary winding, said energizing means including a timer which supplies an enable signal every few seconds to said holding means.

Claim 6

In a DC to AC power inverter of the class B,C,D or E type which includes a battery, at least one power SCR and associated capacitor circuitry, and at least one input winding on a main transformer core, which also has thereon at least one secondary output winding, the improvement comprising self-detecting load demand circuit means coupled to a line from said output winding for cyclically energizing the inverter, for sensing a minimum AC load across said secondary winding, and upon sensing a minimum AC load, for holding said inverter in an energized state until less than a minimum AC load is sensed during an energizing cycle; said load demand circuit means including a current transformer circuit having a primary winding comprised of at least one turn formed by a line from one end of the output secondary winding; and a multi-turn secondary winding, such that a load current flowing through said line generates a voltage across said secondary winding; means for cyclically energizing said inverter; means for sensing a load current flowing in the output secondary winding; and, means for holding said inverter in an energized state when and while a minimum load current is flowing through the output secondary winding, said energizing means including a timer which supplies an enable signal every few seconds to said holding means.

Claim 7

The inverter of claim 4 wherein the turns in said multiturn secondary winding are approximately 85 or more times the turns in the primary winding.

Claim 8

The inverter of claim 4 wherein said sensing means include a current transformer having a primary winding coupled in series with the output secondary winding and a secondary winding.

Claim 9

The inverter of claim 6 wherein said sensing means include rectifying means coupled to said secondary winding.

Claim 10

The inverter of claim 7 wherein said rectifying means include a full wave diode bridge rectifying circuit.

Claim 11

The inverter of claim 7 wherein said holding means include at least a portion of an operational amplifier coupled to the output of said rectifying means and a NAND gate having a first input coupled to an output of said operational amplifier, said energizing means being coupled to a second input of said NAND gate and wherein said inverter includes inverter energizing logic circuitry coupled to the output of said NAND gate.

Claim 12

The inverter of claim 9 wherein said energizing means include a timer which supplies an enable signal every few seconds to said second input of said NAND gate.

Claim 13

The inverter of claim 10 wherein said second input of said NAND gate is also coupled to said secondary winding of said current transformer.

Claim 14

The inverter of claim 4 wherein said holding means include an OR gate having one input coupled to the output of said sensing means.

Claim 15

The inverter of claim 12 wherein the output of said OR gate is coupled to inverter logic energizing circuitry.

Claim 16

The inverter of claim 13 wherein said energizing means include a timer circuit having an output coupled to another input of said OR gate for cyclically applying an energizing signal to said OR gate which then outputs an energizing signal to said inverter logic energizing circuitry.

Claim 17

In a DC to AC power inverter of the class B,C,D or E type which includes a battery, at least one power SCR and associated capacitor circuitry, a main transformer core, at least one input winding on the main transformer core, and at least one output secondary winding on the main transformer core, the improvement comprising automatic power factor correction circuitry for supplying full time leading power factor correction to a load, said automatic power factor correction circuitry being sensitive to light reactive loads and including a power factor correction capacitor, switching means in series with said capacitor and operable to place said power factor correction capacitor in parallel with the load on said output secondary winding, a signal source in said inverter producing a signal having a frequency greater than the inverter output frequency, means for differentiating said signal, first circuit means coupled to said differentiated signal and coupled to the voltage across the load, said first circuit means having a dv/dt sensing circuit and an output coupled to said switching means and being operable to operate said switching means to place said power factor correction capacitor in parallel with the load on a trailing edge of a cycle of the inverter output waveform when a dv/dt above a certain threshold dv/dt is sensed by said sensing circuit and second circuit means connected to have an input voltage proportional to an inductive reactive load and an input coupled to said differentiated signal, the output of said second circuit means also being coupled to said switching means, and said second circuit means being operable to operate said switching means to hold said power factor correction capacitor in parallel with the load after the dv/dt sensed by said sensing circuit has fallen below said threshold dv/dt as long as the load is connected to the inverter.

Claim 18

In a DC to AC power inverter of the class B,C,D or E type which includes a battery, at least one power SCR and associated capacitor circuitry, a main transformer core, at least one input winding on the main transformer core, and at least one output secondary winding on the main transformer core, the improvement comprising automatic power factor correction circuitry for supplying full time leading power factor correction to a load, said automatic power factor correction circuitry being sensitive to light reactive loads and including a power factor correction capacitor, switching means in series with said capacitor and operable to place said power factor correction capacitor in parallel with the load on said output secondary winding, a signal source in said inverter producing a signal having a frequency greater than the inverter output frequency, means for differentiating said signal, first circuit means coupled to said differentiated signal and coupled to the voltage across the load, said first circuit means having a dv/dt sensing circuit and an output coupled to said switching means and being operable to operate said switching means to place said power factor correction capacitor in parallel with the load on a trailing edge of a cycle of the inverter output waveform when a dv/dt above a certain threshold dv/dt is sensed by said sensing circuit and second circuit means connected to have an input voltage proportional to an inductive reactive load and an input coupled to said differentiated signal, the output of said second circuit means also being coupled to said switching means, and said second circuit means being operable to operate said switching means to hold said power factor correction capacitor in parallel with the load after the dv/dt sensed by said sensing circuit has fallen below said threshold dv/dt as long as the load is connected to the inverter.

Claim 19

The inverter of claim 15 wherein said first circuit means includes a NAND gate having one input coupled to said sensing circuit and another input coupled to said differentiated signal.

Claim 20

The inverter of claim 15 wherein said sensing circuit includes an isolating transformer and a capacitor and potentiomater connected across the secondary of said isolating transformer, a wiper of said potentiometer being coupled through a rectifying diode to one input of said first circuit means.

Claim 21

The inverter of claim 17 wherein said first circuit means include a NAND gate having one input coupled to said sensing circuit and another input coupled to said differentiated signal.

Claim 22

The inverter of claims 16 or 18 wherein said first circuit means include a fast attack, slow release circuit coupled to the output of said NAND gate for lengthening the output pulse from said NAND gate supplied to said switching means.

Claim 23

The inverter of claim 15, further comprising a deQing resistor in series with said power factor correction capacitor and said switching means.

Claim 24

The inverter of claim 20, further comprising a isolating resistance connected in parallel with said switching means and in series with said deQing resistor and power factor correction capacitor.

Claim 25

The inverter of claim 21 wherein said switching means include a relay having normally relay contacts each connected to one side of said isolating resistance, said relay, being operable to close said contacts to short circuit said isolating resistance, and said relay having a coil coupled in series with a power source through an emitter and collector of a transistor device, said switching means further including a gate having an output coupled to the base of said transistor device.

Claim 26

The inverter of claim 21 wherein said switching means include a relay having normally open relay contacts each connected to one side of said isolating resistance, said relay, when energized, being operable to close said relay contacts to short circuit said isolating resistance, and said relay having a coil coupled in series with a power source through the emitter and collector of a transistor device and said switching means further including a NAND gate having an output coupled to the base of said transistor device and an input coupled to said first circuit means.

Claim 27

The inverter of claim 23 wherein said rectifying circuit is a full wave diode rectifying bridge.

Claim 28

The inverter of claim 20 wherein said second circuit means include an isolating transformer having a primary coupled across said deQing resistor, and a full wave rectifying circuit coupled across said secondary of said isolating transformer.

Claim 29

The inverter of claim 25 wherein said output of said rectifying circuit is coupled to a potentiometer.

Claim 30

The inverter of claim 26 wherein said second circuit means include a NAND gate having one input coupled to the output of said comparator and another input coupled to said differentiated signal.

Claim 31

The inverter of claim 27 wherein said second circuit means include a one shot circuit having an input coupled to the output of said NAND gate and having an output coupled to said switching means.

Claim 32

The inverter of claim 27 wherein said switching means include a relay having relay contacts each connected to one side of said isolating resistance, said relay being operable to close said relay contacts to short circuit said isolating resistance, and said relay having a coil coupled in series with a power source through a transistor device and said switching means further including a NAND gate having an output coupled to the base of said transistor device and an input coupled to the output of said one short circuit.

Claim 33

The inverter of claim 25 wherein said second circuit means include a comparator having an input coupled to said rectifying circuit and another input connected to a reference voltage.

Claim 34

The inverter of claim 15 wherein said signal source frequency is twice the inverter frequency.

Claim 35

The inverter of claim 15 wherein said signal source produces a 120 Hz signal and said inverter frequency is 60 Hz.

Claim 36

The inverter of claim 15 wherein said second circuit means include an isolating transformer having a primary receiving said input voltage, and a full wave rectifying circuit coupled across said secondary of said isolating transformer.

Claim 37

The inverter of claim 33 wherein said rectifying circuit is a full wave diode rectifying bridge.

Claim 38

The inverter of claim 33 wherein said rectifying circuit is coupled to a potentiometer.

Claim 39

The inverter of claim 33 wherein said second circuit means include a comparator having an input coupled to said rectifying circuit and another input connected to a reference voltage.

Claim 40

The inverter of claim 36 wherein said second circuit means include a NAND gate having one input coupled to the output of said comparator and another input coupled to said differentiated signal.

Claim 41

The inverter of claim 37 wherein said second circuit means include a one shot circuit having an input coupled to the output of said NAND gate and having an output coupled to said switching means.

Claim 42

In a DC to AC power inverter of the class B,C,D or E type which includes a battery, at least one power SCR and associated capacitor circuitry, at least one input winding on a main transformer core, the input winding requiring a quiescent current to establish operating current for capacitor commutation charge and the transformer core having at least one secondary output winding, the improvement comprising: circuit means including an isolated feedback winding on the main transformer and rectifying means coupled between said feedback winding and the battery for feeding current generated by the quiescent current back to the battery, self-detecting load demand circuit means coupled to a line from said output winding for cyclically energizing the inverter, for sensing a minimum AC load across said secondary winding, and upon sensing a minimum AC load, for holding said inverter in an energized state until less than a minimum AC load is sensed during an energizing cycle; and automatic power factor correction circuitry for supplying full time leading power factor correction to a load, said automatic power factor correction circuitry being sensitive to light reactive loads.

Claim 43

In a DC to AC power inverter of the class B,C,D or E type which includes a battery, at least one power SCR and associated capacitor circuitry, at least one input winding on a main transformer core, the input winding requiring a quiescent current to establish operating current for capacitor commutation charge and the transformer core having at least one secondary output winding, the improvement comprising: circuit means including an isolated feedback winding on the main transformer and rectifying means coupled between said feedback winding and the battery for feeding current generated by the quiescent current back to the battery, self-detecting load demand circuit means coupled to a line from said output winding for cyclically energizing the inverter, for sensing a minimum AC load across said secondary winding, and upon sensing a minimum AC load, for holding said inverter in an energized state until less than a minimum AC load is sensed during an energizing cycle; and automatic power factor correction circuitry for supplying full time leading power factor correction to a load, said automatic power factor correction circuitry being sensitive to light reactive loads.