Patent EP0239225A2 successfully refreshed from Google Patents.
US4451794A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Phase comparator
Assignee: Sony Corp
•
Filing: 1982-03-29
•
Granted: 1984-05-29
•
Expires: 2002-03-29
Abstract
Abstract A phase comparator includes a first signal input terminal supplied with a reference signal, a second signal input terminal supplied with an input signal to be compared with the reference signal, a first gate circuit having a pair of input terminals and an output terminal, one of the pair of input terminals of which is connected to the first signal input terminal, a second gate circuit having a pair of input terminals and an output terminal, one of the pair of input terminals of which is connected to the second signal input terminal, a first bi-stable circuit having set, reset and output terminals, the set terminal of which is connected to the output terminal of the first gate circuit, a second bi-stable circuit having set, reset and output terminals, the set terminal of which is connected to the output terminal of the second gate circuit, and first and second gate control circuits connected between the other input terminals of the first and second gate circuits and the output terminals of the first and second bi-stable circuits operative to open one of the first and second gate circuit alternately. The output signal proportional to the phase difference between the input signal and the reference signal is produced at one of the output terminals of the first and second bi-stable circuit in accordance with whether the input signal phase-advances more than the reference signal or not.
Inventors
- 👤 Takaaki Yamada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 23:39
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03D; H03D13/00; H03D13/003; H03D13/004; G; G01; G01R; G01R25/00; G06; G06G; G06G7/00; G06G7/12; G06G7/26
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
368 words
A phase comparator comprising: a first signal input terminal supplied with a reference signal; a second signal input terminal supplied with an input signal to be compared with said reference signal; a first trigger pulse oscillator having an input and an output, the input of which is connected to said first signal input terminal to produce a trigger pulse having a predetermined pulse width at its output; a second trigger pulse oscillator having an input and an output, the input of which is connected to said second signal input terminal to produce a trigger pulse having a predetermined pulse width at its output; a first gate circuit means having a pair of input terminals and an output terminal, one of the pair of input terminals of which is connected to the output of said first trigger pulse oscillator; a second gate circuit means having a pair of input terminals and an output terminal, one of the pair of input terminals of which is connected to the output of said second trigger pulse oscillator; a first bi-stable circuit means having set and reset signal input terminals, and non-inverted and inverted output terminals, the set signal input terminal of which is connected to the output terminal of said first gate circuit means; a second bi-stable circuit means having set and reset signal input terminals, and non-inverted and inverted output terminals, the set signal input termnal of which is connected to the output terminal of said second gate circuit means; a first gate control means connected between the inverted output terminal of said second bi-stable circuit means and the other of the pair of the input terminals of said first gate circuit means; a second gate control means connected between the inverted output terminal of said first bi-stable circuit means and the other of the pair of the input terminals of said second gate circuit means; a first resetting means for supplying the reference signal of said first signal input terminal to the reset signal input terminal of said second bi-stable circuit means; and a second resetting means for supplying the input signal of said second signal input terminal to the reset signal input terminal of said first bi-stable circuit means.
Claim 2
Dependent Claim
368 words
A phase comparator comprising: a first signal input terminal supplied with a reference signal; a second signal input terminal supplied with an input signal to be compared with said reference signal; a first trigger pulse oscillator having an input and an output, the input of which is connected to said first signal input terminal to produce a trigger pulse having a predetermined pulse width at its output; a second trigger pulse oscillator having an input and an output, the input of which is connected to said second signal input terminal to produce a trigger pulse having a predetermined pulse width at its output; a first gate circuit means having a pair of input terminals and an output terminal, one of the pair of input terminals of which is connected to the output of said first trigger pulse oscillator; a second gate circuit means having a pair of input terminals and an output terminal, one of the pair of input terminals of which is connected to the output of said second trigger pulse oscillator; a first bi-stable circuit means having set and reset signal input terminals, and non-inverted and inverted output terminals, the set signal input terminal of which is connected to the output terminal of said first gate circuit means; a second bi-stable circuit means having set and reset signal input terminals, and non-inverted and inverted output terminals, the set signal input termnal of which is connected to the output terminal of said second gate circuit means; a first gate control means connected between the inverted output terminal of said second bi-stable circuit means and the other of the pair of the input terminals of said first gate circuit means; a second gate control means connected between the inverted output terminal of said first bi-stable circuit means and the other of the pair of the input terminals of said second gate circuit means; a first resetting means for supplying the reference signal of said first signal input terminal to the reset signal input terminal of said second bi-stable circuit means; and a second resetting means for supplying the input signal of said second signal input terminal to the reset signal input terminal of said first bi-stable circuit means.
Claim 3
Dependent Claim
32 words
A phase comparator according to claim 1, in which said first gate circuit means comprises a first AND gate circuit, and said second gate circuit means comprises a second AND gate circuit.
Claim 4
Dependent Claim
90 words
A phase comparator according to claim 1, in which said first trigger pulse oscillator comprises a first inverter having an input and an output, the input of which is connected to said first signal input terminal and a NOR circuit having a pair of inputs and an output, the inputs of which are connected to said first signal input terminal and the output of the first inverter, respectively, and the output of which is connected to the one of the pair of input terminals of said first AND gate circuit.
Claim 5
Dependent Claim
90 words
A phase comparator according to claim 3, in which said second trigger pulse oscillator comprises a second inverter having an input and an output, the input of which is connected to said second signal input terminal and a NOR circuit having a pair of inputs and an output, the inputs of which are connected to said second signal input terminal and the output of said second inverter, respectively, and the output of which is connected to the one of the pair of input terminals of said second AND gate circuit.
Claim 6
Dependent Claim
48 words
A phase comparator according to claim 1 further including a first inverter having an input and an output, the input of which is connected to said first signal input terminal, and the output of which is connected to a further input terminal of said first AND gate circuit.
Claim 7
Dependent Claim
48 words
A phase comparator according to claim 5 further including a second inverter having an input and an output, the input of which is connected to said second signal input terminal and the output of which is connected to a further input terminal of said second AND gate circuit.
Claim 8
Dependent Claim
27 words
A phase comparator according to claim 6, in which said first resetting means comprises a first trigger pulse oscillator including an inverter and an AND gate circuit.
Claim 9
Dependent Claim
27 words
A phase comparator according to claim 7, in which said second resetting means comprises a second trigger pulse oscillator including an inverter and an AND gate circuit.
Claim 10
Dependent Claim
20 words
A phase comparator according to claim 8, in which said first flip-flop circuit comprises a pair of NOR gate circuits.
Claim 11
Dependent Claim
20 words
A phase comparator according to claim 9, in which said second flip-flop circuit comprises a pair of NOR gate circuits.
Claim 12
Dependent Claim
40 words
Apparatus according to claim 1, including a trigger pulse generator interconnected between said first signal input terminal and said first gate circuit, and a second trigger input generator interconnected between said second signal input terminal and said second gate circuit.
Claim 13
Dependent Claim
43 words
Apparatus according to claim 11, wherein each of said trigger pulse generator generates a trigger pulse of predetermined width, said width being short in comparison to the delay of said RS flip-flops in producing a Q output in response to a reset signal.
Claim 14
Dependent Claim
210 words
A phase comparator comprising: a first signal input terminal adapted to receive a reference signal; a second signal input terminal adapted to receive an input signal to be compared with said reference signal; first and second RS flip-flops, each having unclocked set and reset inputs and complementary outputs Q and Q 2 ; a first gate circuit having a pair of input terminals and an output terminal, the output terminal being connected to the set input of said first RS flip-flop, and said pair of input terminals being connected respectively to receive said reference signal and the Q signal from said second RS flip-flop; a second gate circuit having a pair of input terminals and an output terminal, the output terminal of the second gate circuit being connected to the set input of said second RS flip-flop, and the input terminals of said second gate circuit being connected respectively to receive said input signal and the Q output of said first RS flip-flop; first reset means for supplying a reset signal to the reset input of said first RS flip-flop in response to said input signal; and second reset means for supplying a reset signal to the reset input of said second RS flip-flop in response to said input signal.
Claim 15
Dependent Claim
210 words
A phase comparator comprising: a first signal input terminal adapted to receive a reference signal; a second signal input terminal adapted to receive an input signal to be compared with said reference signal; first and second RS flip-flops, each having unclocked set and reset inputs and complementary outputs Q and Q 2 ; a first gate circuit having a pair of input terminals and an output terminal, the output terminal being connected to the set input of said first RS flip-flop, and said pair of input terminals being connected respectively to receive said reference signal and the Q signal from said second RS flip-flop; a second gate circuit having a pair of input terminals and an output terminal, the output terminal of the second gate circuit being connected to the set input of said second RS flip-flop, and the input terminals of said second gate circuit being connected respectively to receive said input signal and the Q output of said first RS flip-flop; first reset means for supplying a reset signal to the reset input of said first RS flip-flop in response to said input signal; and second reset means for supplying a reset signal to the reset input of said second RS flip-flop in response to said input signal.
Claim 16
Dependent Claim
17 words
Apparatus according to claim 13, wherein the set and reset inputs of said RS flip-flops operate asynchronisly.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-05-29 | 1987-11-28 | 1988-05-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-05-29 | 1991-11-28 | 1992-05-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-05-29 | 1995-11-28 | 1996-05-29 | $7700.00 | Window Closed / Lapsed |