Speech synthesis system with parameter look up table

Claim 2

A speech synthesis system comprising: first memory means having a plurality of digital speech data stored therein at a plurality of selected address locations, each speech data having a first predetermined number of bits; second memory means storing a plurality of digital sets of first address data from which words in a human language may be derived for speech synthesis, each of said sets off first address data including first address data sequentially stored in said second memory means, and each first address data having fewer bits than said first predetermined number of bits of each said speech data stored in said first memory means and corresponding to a selected one address location within said first memory means; third memory means operably coupled to said first and second memory means and having a plurality of second address data stored therein, each of said second address data corresponding to a selected one of said plurality of sets of first address data stored in said second memory means; and speech synthesis means for converting digital speech data into audible human speech, said speech synthesis means being coupled to said first memory means and at least operably associated with said third memory means for selectively receiving digital speech data from said first memory means in response to accessing of one said selected set of first address data from said second memory means as determined by a said second address data from said third memory means to which said one selected set of first address data corresponds.

Claim 3

A speech synthesis system according to claim 1, wherein said plurality of digital speech data stored in said first memory means includes digital speech data representative of pitch, energy and reflection coefficients.

Claim 4

A speech synthesis system comprising: first memory means having a plurality of digital speech data stored therein at a plurality of selected address locations, each speech data having a first predetermined number of bits; second memory means storing a plurality of digital sets of first address data from which words in a human language may be derived for speech synthesis, each of said sets of first address data including first address data sequentially stored in said second memory means, and each first address data having fewer bits than said first predetermined number of bits of each said speech data stored in said first memory means and corresponding to a selected one address location within said first memory means; controller means operably coupled to said first and second memory means and including third memory means in which a plurality of second address data is stored, each of said second address data corresponding to a selected one of said plurality of sets of first address data stored in said second memory means; and speech synthesis means for converting digital speech data into audible human speech, said speech synthesis means being coupled to said first memory means and at least operably associated with said controller means for selectively receiving digital speech data from said first memory means in response to accessing of one said selected set of first address data from said second memory means as determined by a said second address data from said third memory means of said controller means to which said one selected set of first address data corresponds.

Claim 5

A speech synthesis system comprising: first memory means having a plurality of digital speech data stored therein at a plurality of selected address locations, each speech data having a first predetermined number of bits; second memory means storing a plurality of digital sets of first address data from which words in a human language may be derived for speech synthesis, each of said sets of first address data including first address data sequentially stored in said second memory means, and each first address data having fewer bits than said first predetermined number of bits of each said speech data stored in said first memory means and corresponding to a selected one address location within said first memory means; controller means operably coupled to said first and second memory means and including third memory means in which a plurality of second address data is stored, each of said second address data corresponding to a selected one of said plurality of sets of first address data stored in said second memory means; and speech synthesis means for converting digital speech data into audible human speech, said speech synthesis means being coupled to said first memory means and at least operably associated with said controller means for selectively receiving digital speech data from said first memory means in response to accessing of one said selected set of first address data from said second memory means as determined by a said second address data from said third memory means of said controller means to which said one selected set of first address data corresponds.

Claim 6

A speech synthesis system according to claim 3, wherein said plurality of digital speech data stored in said first memory means includes digital speech data representative of pitch, energy and reflection coefficients.

Claim 7

A speech synthesis system comprising: first memory means having a plurality of digital speech data stored therein at a plurality of selected address locations, each speech data having a first predetermined number of bits; second memory means storing a plurality of digital sets of first address data from which words in a human language may be derived for speech synthesis, each of said sets of first address data including first address data sequentially stored in said second memory means, and each first address data having fewer bits than said first predetermined number of bits of each said speech data stored in said first memory means and corresponding to a selected one address location within said first memory means; third memory means operably coupled to said first and second memory means and having a plurality of second address data stored therein, each of said second address data corresponding to a selected one of said plurality of sets of first address data stored in said second memory means; speech synthesis means for converting digital speech data into audible human speech, said speech synthesis means being coupled to said first memory means and at least operably associated with said third memory means for selectively receiving digital speech data from said first memory means; controller means operably coupled to said first and second memory means and including means for recalling a second address data from said third memory means, means for recalling said set of first address data from said second memory means corresponding to said recalled second addres data, and means for selectively recalling said digital speech data from said first memory means corresponding to said recalled set of first address data from said second memory means; and said speech synthesis means reconversion into audible human speech.

Claim 8

A speech synthesis system comprising: first memory means having a plurality of digital speech data stored therein at a plurality of selected address locations, each speech data having a first predetermined number of bits; second memory means storing a plurality of digital sets of first address data from which words in a human language may be derived for speech synthesis, each of said sets of first address data including first address data sequentially stored in said second memory means, and each first address data having fewer bits than said first predetermined number of bits of each said speech data stored in said first memory means and corresponding to a selected one address location within said first memory means; third memory means operably coupled to said first and second memory means and having a plurality of second address data stored therein, each of said second address data corresponding to a selected one of said plurality of sets of first address data stored in said second memory means; speech synthesis means for converting digital speech data into audible human speech, said speech synthesis means being coupled to said first memory means and at least operably associated with said third memory means for selectively receiving digital speech data from said first memory means; controller means operably coupled to said first and second memory means and including means for recalling a second address data from said third memory means, means for recalling said set of first address data from said second memory means corresponding to said recalled second addres data, and means for selectively recalling said digital speech data from said first memory means corresponding to said recalled set of first address data from said second memory means; and said speech synthesis means reconversion into audible human speech.

Claim 9

A speech synthesis system comprising: first memory means having a plurality of digital speech data stored therein at a plurality of selected address locations, each speech data having a first predetermined number of bits; second memory means storing a plurality of digital sets of first encoded speech data in the form of first address data from which words in a human language may be derived for speech synthesis, each of said sets of first address data including first address dat sequentially stored in said second memory means, and each first address data having fewer bits than said first predetermined number of bits of each said speech data stored in said first memory means and corresponding to a gth, wherein said variable length data frames include encoded speech parameters of variable length which are representative of itch, energy and filter coefficients; to accessing of one said selected set of first address data from said second memory means as received by said input means; and controller means operably coupled to said first and second memory means and to said input means and including third memory means in which a plurality of second encoded speech data in the form of second address data is stored, each of said second address data corresponding to a selected one of said plurality of sets of first address data stored in said second memory means, the accessing of said one selected set of first address data from said second memory means being determined by a said second address data from said third memory means of said controller means to which said one selected set of first address data corresponds.

Claim 10

A speech synthesis system comprising: first memory means having a plurality of digital speech data stored therein at a plurality of selected address locations, each speech data having a first predetermined number of bits; second memory means storing a plurality of digital sets of first encoded speech data in the form of first address data from which words in a human language may be derived for speech synthesis, each of said sets of first address data including first address dat sequentially stored in said second memory means, and each first address data having fewer bits than said first predetermined number of bits of each said speech data stored in said first memory means and corresponding to a gth, wherein said variable length data frames include encoded speech parameters of variable length which are representative of itch, energy and filter coefficients; to accessing of one said selected set of first address data from said second memory means as received by said input means; and controller means operably coupled to said first and second memory means and to said input means and including third memory means in which a plurality of second encoded speech data in the form of second address data is stored, each of said second address data corresponding to a selected one of said plurality of sets of first address data stored in said second memory means, the accessing of said one selected set of first address data from said second memory means being determined by a said second address data from said third memory means of said controller means to which said one selected set of first address data corresponds.

Claim 11

A speech synthesis system according to claim 1 wherein at least one address location within said first memory means corresponds to a plurality of first address data.

Claim 12

A speech synthesis system according to claim 1, wherein: each set of first address data contained in said second memory means includes a plurality of multifield data frames, each field of said data frames being composed of first address data.

Claim 13

A speech synthesis system according to claim 5 wherein at least one address location within said first memory means corresponds to a plurality of first address data.

Claim 14

A speech synthesis system according to claim 5 wherein said means for recalling a second address data includes means for randomly selecting a second address data.

Claim 15

A speech synthesis system according to claim 5 further comprising means for sensing a start up of said speech synthesis system and wherein said means for recalling a second address data is responsive to said start-up sensing means

Claim 16

A speech synthesis system according to claim 5 further comprising operator input means for receiving an operator input; and said means for recalling a second address data being responsive to said operator input.