US4449197A
Expired / Lapsed
US
⏱️ 0.0 years remaining
One-bit full adder circuit
Assignee: AT&T Inc
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Filing: 1982-03-10
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Granted: 1984-05-15
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Expires: 2002-03-10
Abstract
Abstract The present invention is a one-bit full adder circuit having a fast carry. The circuit may be implemented using integrated injection logic in which case the circuit comprises six NAND gates and two wired AND gates. Advantageously, there is only a single gate delay in the carry path.
Inventors
- 👤 James L. Henry
- 👤 Wendy A. Stocker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 15:09
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/501; G06F2207/00; G06F2207/38; G06F2207/3804; G06F2207/386; G06F2207/3876
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
207 words
A one-bit full adder circuit comprising: means forming a first NAND gate operatively connected for receiving first and second operand input signals and for producing a first output signal; means forming a second NAND gate operatively connected for receiving complements of said first and second operand input signals and for producing a second output signal; means forming a third NAND operatively connected for receiving said first and second output signals and for producing a third output signal; means forming a fourth NAND gate operatively connected for receiving a carry input signal and said first and second output signals and for producing a fourth output signal; means forming a fifth NAND gate operatively connected for receiving the complement of said carry input signal and said third output signal and for producing a fifth output signal; means forming a sixth NAND gate operatively connected for receiving said first and fourth output signals and for producing a carry output signal; means forming a first AND gate operatively connected for receiving said first and fourth output signals and for producing the complement of said carry output signal; and means forming a second AND gate operatively connected for receiving said fourth and fifth output signals and for producing a sum output signal.
Claim 2
Dependent Claim
207 words
A one-bit full adder circuit comprising: means forming a first NAND gate operatively connected for receiving first and second operand input signals and for producing a first output signal; means forming a second NAND gate operatively connected for receiving complements of said first and second operand input signals and for producing a second output signal; means forming a third NAND operatively connected for receiving said first and second output signals and for producing a third output signal; means forming a fourth NAND gate operatively connected for receiving a carry input signal and said first and second output signals and for producing a fourth output signal; means forming a fifth NAND gate operatively connected for receiving the complement of said carry input signal and said third output signal and for producing a fifth output signal; means forming a sixth NAND gate operatively connected for receiving said first and fourth output signals and for producing a carry output signal; means forming a first AND gate operatively connected for receiving said first and fourth output signals and for producing the complement of said carry output signal; and means forming a second AND gate operatively connected for receiving said fourth and fifth output signals and for producing a sum output signal.
Claim 3
Dependent Claim
83 words
The single-bit full adder circuit of claim 1 wherein: each of said AND gates is a wired AND gate; and each of said means forming said NAND gates comprises: an npn bipolar transistor having a grounded emitter, a base, and at least one collector, current being selectively injected into said base from pnp transistor means; and a wired AND gate for receiving a plurality of input signals and for producing an output signal which is transmitted to said base of said npn transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-05-15 | 1987-11-14 | 1988-05-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-05-15 | 1991-11-14 | 1992-05-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-05-15 | 1995-11-14 | 1996-05-15 | $7700.00 | Window Closed / Lapsed |