Semiconductor device for driving thermal print heads

Claim 2

A semiconductor device formed on a single semiconductor chip operatively connected to receive a power control signal, comprising: a first circuit activated when power is applied to the semiconductor device, comprising: input buffer circuits; and output driver circuits, operatively connected to said input buffer circuits; and a second circuit, operatively connected to said first circuit, activated only when both power and the power control signal are applied to the semiconductor device, said second circuit comprising a data storing circuit operatively connected to said input buffer circuits and said output driver circuits.

Claim 3

A semiconductor device according to claim 1, wherein said semiconductor device further comprises a power switch circuit, operatively connected to said second circuit, for supplying power to said second circuit, for supplying power to said second circuit only when the power control signal is applied to said power switch circuit.

Claim 4

A semiconductor device according to claim 2, wherein said power switch circuit comprises switching transistors, operatively connected to said data storing circuit, forming a Darlington circuit and turning on and off under the control of said power control signal.

Claim 5

A semiconductor device according to claim 3, wherein said power switch circuit further comprises: a pnp-type emitter follower transistor operatively connected to receive the power control signal and outputting a first signal; an npn-type emitter follower transistor, operatively connected to said pnp-type emitter follower transistor, for receiving the first output signal of said pnp-type emitter follower transistor and outputting a second output signal; and an npn-type inverter transistor, operatively connected to said npn-type emitter follower transistor, for receiving the second output signal of said npn-type emitter follower transistor and outputting a third output signal, wherein said Darlington circuit comprises two npn-type Darlington connected transistors, operatively connected to said npn-type inverter transistor, for receiving the third output signal of said npn-type inverter transistor and switching on and off the power supplied to said second circuit.

Claim 6

A semiconductor device according to claim 2, wherein said power switch circuit is included in said first circuit.

Claim 7

A semiconductor device operatively connected to external circuits, according to claim 5, wherein said input buffer circuits and output driver circuits included in said first circuit are directly connected to the external circuits, and wherein said data storing circuit included in said second circuit is not directly connected to the external circuits.

Claim 8

A semiconductor device according to claim 5, wherein said input buffer circuits are operatively connected to receive input signals and provide output signals, and wherein said data storing circuit comprises a plurality of flip-flip circuits, respectively, operatively connected to said input buffer circuits, having input terminals for receiving the output signals provided by said input buffer circuits and having output terminals operatively connected to said output driver circuits.

Claim 9

A semiconductor device operatively connected to a thermal printer having thermal heads, according to claim 7, wherein said output driver circuits are operatively connected to the thermal heads of the thermal printer.

Claim 10

A semiconductor device according to claim 5, wherein said data storing circuit comprises a shift register including a plurality of cascade-connected flip-flop circuits each having an output terminal and latch circuits each having an output terminal, respectively, operatively connected to said output terminals of said cascade-connected flip-flop circuits.

Claim 11

A semiconductor device according to claim 9, wherein said latch circuits are operatively connected to said output driver circuits.

Claim 12

A semiconductor device formed on a single semiconductor chip, operatively connected to receive a power control signal and operatively connectable to a power supply, comprising: a first circuit made operable when power is applied to the semiconductor device, comprising: input buffer circuits operatively connected to the power supply; output driver circuits operatively connected to said input buffer circuits and the power supply; a clock circuit operatively connected to the power supply and said output driver circuits; and a power switch circuit operatively connected to the power supply and operatively connected to receive the power control signal; and a second circuit, operatively connected to said first circuit, made operable only when both the power control signal and power supply are supplied to the semiconductor device, comprising a data storing circuit operatively connected to said power switch circuit.

Claim 13

A semiconductor device formed on a single semiconductor chip, operatively connected to receive a power control signal and operatively connectable to a power supply, comprising: a first circuit made operable when power is applied to the semiconductor device, comprising: input buffer circuits operatively connected to the power supply; output driver circuits operatively connected to said input buffer circuits and the power supply; a clock circuit operatively connected to the power supply and said output driver circuits; and a power switch circuit operatively connected to the power supply and operatively connected to receive the power control signal; and a second circuit, operatively connected to said first circuit, made operable only when both the power control signal and power supply are supplied to the semiconductor device, comprising a data storing circuit operatively connected to said power switch circuit.

Claim 14

A semiconductor device according to claim 11, wherein said power switch circuit has an input terminal and an output terminal and comprises: a pnp transistor operatively connected to the input terminal; an npn Schottky barrier transistor operatively connected to said pnp transistor; a first npn-transistor operatively connected to said npn Schottky barrier transistor; a second npn transistor operatively connected to said first npn transistor; and a third npn transistor operatively connected to said second npn transistor, forming a Darlington connection with said second npn transistor and the output terminal.

Claim 15

A semiconductor device according to claim 12 wherein said data storing circuit comprises: at least one switching transistor operatively connected to the output terminal of said power switch circuit; and at least one current source operatively connected to said at least one switching transistor and the output terminal of said power switch circuit.