US4446530A
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Fast hadamard transform device
Assignee: Panasonic Holdings Corp
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Filing: 1981-08-05
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Granted: 1984-05-01
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Expires: 2001-08-05
Abstract
Abstract Devices for performing fast Hadamard transforms based upon a predetermined algorithm are provided. A buffer memory (random-access memory) with the capacity equal to the number of components of an input vector to be transformed is provided and is addressed in such a way computation of Hadamard transforms can be performed at faster speeds with a higher degree of efficiency.
Inventors
- 👤 Eiichi Tsuboka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 20:05
CPC Classifications
G; G06; G06F; G06F17/00; G06F17/10; G06F17/14; G06F17/145
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
237 words
In a fast Hadamard transform of order 2 m , where m=1, 2, . . . in which X k (i)=X k-1 (i)+X k-1 (j) and X k (j)=X k-1 (i)-X k-1 (j), where i and j=0, 1, . . . , 2 m- 1 and X k (i) and X k (j) are i-th and j-th elements in the k-th transform step, a fast Hadamard transform device having an addressing means for reading intermediate transformed values into or out of a random-access memory, said device comprising: (a) a binary counter with at least (m-1) bits; (b) a register means for specifying the current transform step and a predetermined bit position of an address in said random access memory for the transform step; and (c) an address specification means which, in the case of deriving the values of the k-th transform step from the results of the (k-1)-th transform step, holds a bit at said specified predetermined bit position of an address in said random-access memory in the logical state S (1 or 0) in the case of reading out of X k (i) but holds in the logical state S, the negation of the logical state S, in the case of reading out of X k-1 (j) or writing of X k (j) and which holds the bits at the remaining bit positions in the same pattern as that of the contents in said binary counter.
Claim 2
Dependent Claim
237 words
In a fast Hadamard transform of order 2 m , where m=1, 2, . . . in which X k (i)=X k-1 (i)+X k-1 (j) and X k (j)=X k-1 (i)-X k-1 (j), where i and j=0, 1, . . . , 2 m- 1 and X k (i) and X k (j) are i-th and j-th elements in the k-th transform step, a fast Hadamard transform device having an addressing means for reading intermediate transformed values into or out of a random-access memory, said device comprising: (a) a binary counter with at least (m-1) bits; (b) a register means for specifying the current transform step and a predetermined bit position of an address in said random access memory for the transform step; and (c) an address specification means which, in the case of deriving the values of the k-th transform step from the results of the (k-1)-th transform step, holds a bit at said specified predetermined bit position of an address in said random-access memory in the logical state S (1 or 0) in the case of reading out of X k (i) but holds in the logical state S, the negation of the logical state S, in the case of reading out of X k-1 (j) or writing of X k (j) and which holds the bits at the remaining bit positions in the same pattern as that of the contents in said binary counter.
Claim 3
Dependent Claim
156 words
A fast Hadamard transform device as set forth in claim 1 wherein said address specification means holds the bits in the 2 0 -th to 2 m-k-1 -th bit positions of an address in said random-access memory in one-to-one correspondence relationships, respectively, with the bits in the 2 m-k+1 -th to 2 m -th positions in said binary counter; and holds the bits in the 2 m-k+1 -th to 2 m -th bit positions of said address in one-to-one correspondence relationships, respectively with the bits in the 2 m-k -th to 2 m-1 -th bit positions in said binary counter; and holds the bit in the 2 m-k -th bit position of said address in the logical state S in the case of reading out of X k-1 (i) or writing of X k (i) or in the logical state S in the case of reading out X k-1 (j) or writing of X k (j).
Claim 4
Dependent Claim
157 words
A fast Hadamard transform device as set forth in claim 1 wherein said address specification means holds the bits in the 2 0 -th to 2 k-2 -th bit positions of an address in said random-access memory in one-to-one correspondence relationships, respectively, with the bits in the 2 0 -th to 2 k-2 -th bit positions of said binary counter; holds the bits in the 2 k -th to 2 m -th bit positions of said address in one-to-one correspondence relationships, respectively, with the bits in the 2 k-1 -th to 2 m-1 -th bit positions of said binary counter; and holds the bit in the 2 k-1 -th bit position of said address in the logical state S in the case of reading out of X k-1 (i) or writing of X k (i) or in the logical state S in the case of reading out of X k-1 (j) or writing of X k (j).
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-05-01 | 1987-10-31 | 1988-05-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-05-01 | 1991-10-31 | 1992-05-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-05-01 | 1995-10-31 | 1996-05-01 | $7700.00 | Window Closed / Lapsed |