US4446475A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Means and method for disabling access to a memory
Assignee: Motorola Solutions Inc
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Filing: 1981-07-10
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Granted: 1984-05-01
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Expires: 2001-07-10
Abstract
Abstract An integrated circuit chip having a digital memory is provided wherein direct access to at least a portion of the memory is prevented. Contact pads having coupling lines to couple the contact pads to the memory bus are provided. A security code can be programmed into a portion of the memory during wafer probe and test. When the integrated circuit chip is removed from the wafer the coupling lines between the contact pads and the memory bus are destroyed since the coupling lines are made to extend off of the chip.
Inventors
- 👤 Anil Gercekci
- 👤 Heinz B. Maeder
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 02:59
CPC Classifications
G; G07; G07F; G07F7/00; G07F7/08; G07F7/10; G07F7/1008; G06; G06K; G06K19/00; G06K19/06; G06K19/067; G06K19/07; G06K19/073; G06K7/00; G06K7/0095; G06Q; G06Q20/00; G06Q20/30; G06Q20/34; G06Q20/341; G06Q20/38; G06Q20/40; G06Q20/409; G06Q20/4097; G11; G11C; G11C8/00; G11C8/20; H; H10; H10W; H10W72/00
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
101 words
A semiconductor chip having a digital memory wherein direct access to at least a portion of the memory is prevented, the semiconductor chip having been formed on a wafer and then separated therefrom, comprising: contact pads for making electrical contact to the memory; memory bus for carrying data to and from the at least a portion of the memory; and means coupling some of the contact pads to the memory bus, the means having a portion thereof extending off the semiconductor chip to disable the means after the semiconductor chip is separated from the wafer from which the chip was made.
Claim 2
Dependent Claim
101 words
A semiconductor chip having a digital memory wherein direct access to at least a portion of the memory is prevented, the semiconductor chip having been formed on a wafer and then separated therefrom, comprising: contact pads for making electrical contact to the memory; memory bus for carrying data to and from the at least a portion of the memory; and means coupling some of the contact pads to the memory bus, the means having a portion thereof extending off the semiconductor chip to disable the means after the semiconductor chip is separated from the wafer from which the chip was made.
Claim 3
Dependent Claim
119 words
A semiconductor chip having a digital memory wherein direct access to at least a portion of the memory is prevented, comprising: contact pads for making electrical contact to the memory; memory bus for carrying data to and from the memory; and means coupling the contact pads to the memory bus, the means having a portion thereof extending off the semiconductor chip so that the means becomes disabled when the semiconductor chip is separated from a wafer from which the chip was made wherein the means is a transistor coupled between the contact pad and the memory bus, the transistor having a control electrode coupled to a control signal by a line wherein the line extends off the semiconductor chip.
Claim 4
Dependent Claim
119 words
A semiconductor chip having a digital memory wherein direct access to at least a portion of the memory is prevented, comprising: contact pads for making electrical contact to the memory; memory bus for carrying data to and from the memory; and means coupling the contact pads to the memory bus, the means having a portion thereof extending off the semiconductor chip so that the means becomes disabled when the semiconductor chip is separated from a wafer from which the chip was made wherein the means is a transistor coupled between the contact pad and the memory bus, the transistor having a control electrode coupled to a control signal by a line wherein the line extends off the semiconductor chip.
Claim 5
Dependent Claim
27 words
The semiconductor chip of claim 1 wherein the contact pad is coupled to the memory bus by a line wherein the line extends off the semiconductor chip.
Claim 6
Dependent Claim
154 words
A semiconductor memory chip made from a wafer along with a plurality of other semiconductor memory chips wherein an adjacent memory chip forms a pair with the semiconductor memory chip, at least one contact pad located on the semiconductor memory chip, at least one contact pad located on the adjacent memory chip, a first line connecting a portion of a memory on the semiconductor memory chip to the contact pad on the adacent memory chip without connecting to any contact pad on the semiconductor memory chip, and a second line connecting a portion of a memory on the adjacent memory chip to the at least one contact pad on the semiconductor memory chip without connecting to any contact pad on the adjacent memory chip to inhibit further access to the portion of the memory on the pair of memory chips by way of the at least one contact pads when the chips are separated.
Claim 7
Dependent Claim
154 words
A semiconductor memory chip made from a wafer along with a plurality of other semiconductor memory chips wherein an adjacent memory chip forms a pair with the semiconductor memory chip, at least one contact pad located on the semiconductor memory chip, at least one contact pad located on the adjacent memory chip, a first line connecting a portion of a memory on the semiconductor memory chip to the contact pad on the adacent memory chip without connecting to any contact pad on the semiconductor memory chip, and a second line connecting a portion of a memory on the adjacent memory chip to the at least one contact pad on the semiconductor memory chip without connecting to any contact pad on the adjacent memory chip to inhibit further access to the portion of the memory on the pair of memory chips by way of the at least one contact pads when the chips are separated.
Claim 8
Independent Claim
79 words
A method of disabling direct access to at least a portion of a memory comprising: providing at least one contact pad on a semiconductor chip wherein the memory is located; providing coupling means to the at least one contact pad to couple the contact pad to the at least a portion of the memory; providing lines as a portion of the coupling means, the lines extending off of the semiconductor chip; disabling the coupling means by severing the lines.
Claim 9
Independent Claim
79 words
A method of disabling direct access to at least a portion of a memory comprising: providing at least one contact pad on a semiconductor chip wherein the memory is located; providing coupling means to the at least one contact pad to couple the contact pad to the at least a portion of the memory; providing lines as a portion of the coupling means, the lines extending off of the semiconductor chip; disabling the coupling means by severing the lines.
Claim 10
Independent Claim
111 words
A method of disabling direct access to at least a portion of a memory located on a semiconductor chip wherein the semiconductor chip is formed on a wafer with at least an adjacent chip also having a memory, the method comprising: providing at least one contact pad on each of the chips; coupling the contact pad on the semiconductor chip to circuitry on the adjacent chip; coupling the contact pad on the adjacent chip to circuitry on the semiconductor chip; and separating the semiconductor chip and the adjacent chip thereby disabling the coupling to the pads which results in interrupting access from the contact pads to a predetermined location in memory.
Claim 11
Independent Claim
111 words
A method of disabling direct access to at least a portion of a memory located on a semiconductor chip wherein the semiconductor chip is formed on a wafer with at least an adjacent chip also having a memory, the method comprising: providing at least one contact pad on each of the chips; coupling the contact pad on the semiconductor chip to circuitry on the adjacent chip; coupling the contact pad on the adjacent chip to circuitry on the semiconductor chip; and separating the semiconductor chip and the adjacent chip thereby disabling the coupling to the pads which results in interrupting access from the contact pads to a predetermined location in memory.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-05-01 | 1987-10-31 | 1988-05-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-05-01 | 1991-10-31 | 1992-05-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-05-01 | 1995-10-31 | 1996-05-01 | $7700.00 | Window Closed / Lapsed |