System for defeating erroneous correction in a digital signal reproducing apparatus

Claim 1

A system for defeating erroneous corrections in a digital signal reproducing apparatus, said system comprising, in combination: reproducing means for reproducing a digital signal sequence from a recording medium, said recording medium having a sequence of digital signals recorded thereon in a plurality of blocks of data, each of said data blocks including a digital signal sequence and an error-detecting cyclical redundancy check word, said digital signal sequence including n m-bit information words W 1 through W n and two error correcting words P and Q which satisfy the following equations: P=W.sub.1 ⊕W.sub.2 ⊕W.sub.3 ⊕ . . . ⊕W.sub.n-1 ⊕W.sub.n and Q=T.sup.n ·W.sub.1 ⊕T.sup.n-1 ·W.sub.2 ⊕ . . . ⊕T.sup.2 ·W.sub.n-1 ⊕T·W.sub.n or Q=T·W.sub.1 ⊕T.sup.2 ·W.sub.2 ⊕ . . . ⊕T.sup.n-1 ·W.sub.n-1 ⊕T.sup.n ·W.sub.n and which are interleaved, where: m and n are integers satisfying a relation 2 m-1 >>n, the symbol "⊕" indicates a modulo-2 addition, and T is a companion matrix of a polynomial 1+g 1 x+g 2 x 2 + . . . +g m-1 x m-1 +x m , said information words W 1 through W n being a digital modulation responsive to an analog information signal and a resultant digital information signal divided into predetermined sections, said error-detecting cyclical redundancy check word indicating a number of erroneous words in each of said blocks made up of interleaved words; memory circuit means for storing the digital signal sequence reproduced from said recording medium by said reproducing means, and for producing a digital signal sequence which includes the information words W 1 through W n and the error correcting words P and Q which are de-interleaved and arranged in an original sequence; correcting circuit means for carrying out adjacent error corrections with respect to the digital signal sequence produced from said memory circuit means by a use of error pointers, and for correcting errors of up to two words in each of a plurality of blocks made up of the de-interleaved words, said error pointers being formed from said error detecting cyclical redundancy check words and indicating erroneous words in each of said blocks made up of de-interleaved words; and digital-to-analog converter means for converting a digital information signal obtained from said correcting circuit means into the original analog information signal, said correcting circuit means calculating partial syndromes S 1 , S 2 , and S 12 according to the following equations: S.sub.1 =P⊕W.sub.1 ⊕W.sub.2 ⊕ . . . ⊕W.sub.n-1 ⊕W.sub.n S.sub.2 =Q⊕T.sup.n ·W.sub.1 ⊕T.sup.n-1 ·W.sub.2 ⊕ . . . ⊕T.sup.2 ·W.sub.n-1 ⊕T·W.sub.n or S.sub.2 =Q⊕T·W.sub.1 ⊕T.sup.2 ·W.sub.2 ⊕ . . . ⊕T.sup.n-1 ·W.sub.n-1 ⊕T.sup.n ·W.sub.n and S.sub.12 =S.sub.1 ⊕T.sup.l-n-1 ·S.sub.2 where: l=1, 2, 3, . . . , n, and said correcting circuit means detecting the erroneous words in units of blocks, which are made up of the de-interleaved words, by use of said error pointers and for stopping said error correction when a number of detected erroneous words in one block, which is made up of the de-interleaved words, is equal to zero or one and all of the calculated partial syndromes S 1 , S 2 , and S 12 , are not equal to , and continuing to stop said error correction (1) until the number of detected erroneous words becomes equal to zero and all of the partial syndromes S 1 , S 2 , and S 12 become equal to or (2) until the number of detected erroneous words becomes equal to zero or one and at least one of the partial syndromes S 1 , S 2 , and S 12 becomes equal to .

Claim 2

A system for defeating erroneous corrections in a digital signal reproducing apparatus, said system comprising, in combination: reproducing means for reproducing a digital signal sequence from a recording medium, said recording medium having a sequence of digital signals recorded thereon in a plurality of blocks of data, each of said data blocks including a digital signal sequence and an error-detecting cyclical redundancy check word, said digital signal sequence including n m-bit information words W 1 through W n and two error correcting words P and Q which satisfy the following equations: P=W.sub.1 ⊕W.sub.2 ⊕W.sub.3 ⊕ . . . ⊕W.sub.n-1 ⊕W.sub.n and Q=T.sup.n ·W.sub.1 ⊕T.sup.n-1 ·W.sub.2 ⊕ . . . ⊕T.sup.2 ·W.sub.n-1 ⊕T·W.sub.n or Q=T·W.sub.1 ⊕T.sup.2 ·W.sub.2 ⊕ . . . ⊕T.sup.n-1 ·W.sub.n-1 ⊕T.sup.n ·W.sub.n and which are interleaved, where: m and n are integers satisfying a relation 2 m-1 >>n, the symbol "⊕" indicates a modulo-2 addition, and T is a companion matrix of a polynomial 1+g 1 x+g 2 x 2 + . . . +g m-1 x m-1 +x m , said information words W 1 through W n being a digital modulation responsive to an analog information signal and a resultant digital information signal divided into predetermined sections, said error-detecting cyclical redundancy check word indicating a number of erroneous words in each of said blocks made up of interleaved words; memory circuit means for storing the digital signal sequence reproduced from said recording medium by said reproducing means, and for producing a digital signal sequence which includes the information words W 1 through W n and the error correcting words P and Q which are de-interleaved and arranged in an original sequence; correcting circuit means for carrying out adjacent error corrections with respect to the digital signal sequence produced from said memory circuit means by a use of error pointers, and for correcting errors of up to two words in each of a plurality of blocks made up of the de-interleaved words, said error pointers being formed from said error detecting cyclical redundancy check words and indicating erroneous words in each of said blocks made up of de-interleaved words; and digital-to-analog converter means for converting a digital information signal obtained from said correcting circuit means into the original analog information signal, said correcting circuit means calculating partial syndromes S 1 , S 2 , and S 12 according to the following equations: S.sub.1 =P⊕W.sub.1 ⊕W.sub.2 ⊕ . . . ⊕W.sub.n-1 ⊕W.sub.n S.sub.2 =Q⊕T.sup.n ·W.sub.1 ⊕T.sup.n-1 ·W.sub.2 ⊕ . . . ⊕T.sup.2 ·W.sub.n-1 ⊕T·W.sub.n or S.sub.2 =Q⊕T·W.sub.1 ⊕T.sup.2 ·W.sub.2 ⊕ . . . ⊕T.sup.n-1 ·W.sub.n-1 ⊕T.sup.n ·W.sub.n and S.sub.12 =S.sub.1 ⊕T.sup.l-n-1 ·S.sub.2 where: l=1, 2, 3, . . . , n, and said correcting circuit means detecting the erroneous words in units of blocks, which are made up of the de-interleaved words, by use of said error pointers and for stopping said error correction when a number of detected erroneous words in one block, which is made up of the de-interleaved words, is equal to zero or one and all of the calculated partial syndromes S 1 , S 2 , and S 12 , are not equal to , and continuing to stop said error correction (1) until the number of detected erroneous words becomes equal to zero and all of the partial syndromes S 1 , S 2 , and S 12 become equal to or (2) until the number of detected erroneous words becomes equal to zero or one and at least one of the partial syndromes S 1 , S 2 , and S 12 becomes equal to .