Full-wave rectifying circuit

Claim 2

A full-wave rectifying circuit comprising: an input terminal for receiving an input signal; a reference potential terminal; a first current conducting path, connected to said input terminal, with means for conducting a first current corresponding to a signal component of a first polarity of said input signal; a first resistor coupled at one end thereof to said reference potential terminal; a second current conducting path, connected to said input terminal, with means for conducting a second current corresponding to a signal component of a second polarity opposite to said first polarity, of the input signal; and a first current mirror circuit having a first current mirror path coupled to said first and second current connecting paths and a second current mirror path coupled to the other end of said resistor for causing a current flow in said resistor equal to the absolute value of the combined currents flowing through said first and second connecting paths.

Claim 3

A full-wave rectifying circuit according to claim 1, wherein said second current conducting path means comprises a second resistor, a first transistor having an emitter-collector path connected in series with said second resistor and a base maintained at a substantially constant potential, and a second current mirror circuit having a third current mirror path connected to said input terminal through said second resistor and said emitter-collector path of said first transistor, and a fourth current mirror path connected to the first current path of said first current mirror circuit.

Claim 4

A full-wave rectifying circuit according to claim 1 or 2, wherein said first current conducting path means has a third resistor and a second transistor having an emitter-collector path connected in series with said third resistor and a base maintained at a substantially constant potnetial.

Claim 5

A full-wave rectifying circuit according to claim 3, wherein said first resistor has a resistance twice that of either said second or said third resistor.

Claim 6

A full-wave rectifying circuit comprising: an input terminal for receiving an input signal; a reference potential terminal; first and second current conducting paths which are connected to the input terminal to conduct currents corresponding to respective signal components of opposite polarities of the input signal supplied to the input terminal, said second current conducting path including a first transistor having a base connected to said input terminal; a first resistor connected at a first end thereof to said reference potential terminal; a first current mirror circuit having first and second current mirror paths which are respectively connected to said first current conducting path and a second end of said first resistor to conduct through said first resistor a current corresponding to a current flowing through said first current conducting path; and a second transistor having a base connected to the second end of said first resistor and having an emitter-collector path connected in parallel with that of said first transistor.

Claim 7

A full-wave rectifying circuit comprising: an input terminal for receiving an input signal; a reference potential terminal; first and second current conducting paths which are connected to the input terminal to conduct currents corresponding to respective signal components of opposite polarities of the input signal supplied to the input terminal, said second current conducting path including a first transistor having a base connected to said input terminal; a first resistor connected at a first end thereof to said reference potential terminal; a first current mirror circuit having first and second current mirror paths which are respectively connected to said first current conducting path and a second end of said first resistor to conduct through said first resistor a current corresponding to a current flowing through said first current conducting path; and a second transistor having a base connected to the second end of said first resistor and having an emitter-collector path connected in parallel with that of said first transistor.

Claim 8

A full-wave rectifying circuit according to claim 5, wherein said first current conducting path includes a second resistor and a third transistor having an emitter-collector path connected in series with said second resistor between said input terminal and said first current mirror path and having a base maintained at a substantially constant potential.

Claim 9

A full-wave rectifying circuit according to claim 6, wherein said first and second resistors have the same resistance.

Claim 10

A level sensing circuit comprising: logarithmic amplifying means for producing an output signal corresponding to the logarithm of an input signal; first and second current conducting paths connected to an output terminal of said logarithmic amplifying means for conducting currents corresponding to signal components of opposite polarities of an output signal from said logarithmic amplifying means; a first resistor connected at a first end thereof to a reference terminal; a current mirror circuit which is connected to said first and second current conducting paths and a second end of said first resistor to conduct through said first resistor a current corresponding to the absolute value of a combination of currents flowing through said first and said second current conducting paths; and a smoothing circuit which is connected to said first resistor to smooth a voltage signal produced from said first resistor.

Claim 11

A level sensing circuit comprising: logarithmic amplifying means for producing an output signal corresponding to the logarithm of an input signal; first and second current conducting paths connected to an output terminal of said logarithmic amplifying means for conducting currents corresponding to signal components of opposite polarities of an output signal from said logarithmic amplifying means; a first resistor connected at a first end thereof to a reference terminal; a current mirror circuit which is connected to said first and second current conducting paths and a second end of said first resistor to conduct through said first resistor a current corresponding to the absolute value of a combination of currents flowing through said first and said second current conducting paths; and a smoothing circuit which is connected to said first resistor to smooth a voltage signal produced from said first resistor.

Claim 12

A level sensing circuit according to claim 8, wherein each of said first and second current conducting paths includes a further resistor and a transistor having an emitter-collector path connected in series with said further resistor between the output terminal of said logarithmic amplifying means and said current mirror circuit.

Claim 13

A level sensing circuit according to claim 9, wherein said current mirror circuit has a first current mirror section having first and second current mirror paths which are respectively connected to said first current conducting path and said first resistor, and a second current mirror section having second and third current mirror paths which are respectively connected to said second current conducting path and said first current mirror path.

Claim 14

A level sensing circuit according to claim 8 or 9, wherein said first resistor has a resistance twice that of said resistor of either said first or said second current path.