Variable phase lock control

Claim 2

A variable phase lock control comprising: (a) first storage means for digitally storing a representation of a first signal forming a substantially full cycle of a first predetermined waveform, the adresses of sequential elements of said first signal being sequential, (b) means for generating a first address signal designating the addresses of said first signal elements and addressing the first storage means sequentially and cyclically to read out the stored first signal, (c) second means for digitally storing a representation of a second signal forming a substantially full cycle of a second predetermined waveform, the addresses of sequential elements of said second signal being sequential, the number of elements of the first and second signals being similar, (d) means for generating a digital signal having a value between zero and the number of elements of said first and second signals, (e) means for adding said digital signal and the addresses of the first signal elements to provide a second address signal, (f) means for addressing the second storage means sequentially and cyclically with the second address signal to read out the stored second signal, whereby the read out first signal and the read out second signal have a phase relationship dependent on the value of the digital signal.

Claim 3

A variable phase lock control as defined in claim 1, in which the digital signal is established by manual control means.

Claim 4

A variable phase lock control as defined in claim 1, in which the first and second means for storing said first and second signals are Read Only Memories (ROMs).

Claim 5

A variable phase lock control as defined in claim 3, in which the ROMs are each adapted to output signal representations of sequential elements of sine waves upon being progressively addressed with sequential digital addresses.

Claim 6

A variable phase lock control as defined in claim 1, 3 or 4 in which the digital signal is established by a binary signal generator operated from a source of control signals.

Claim 7

A variable phase lock control comprising: (a) a first oscillator, (b) a first counter connected to the output of the oscillator for counting output pulses from said oscillator and generating sequential first address signals corresponding to the number of said pulses counted, including means for resetting said counter after a predetermined number of pulses, (c) a first ROM, having digital representations of sequential elements of a substantially full cycle of a first predetermined signal waveform stored at sequential memory addresses, its address input being connected to the output of the first counter and adapted to output said digital representations sequentially upon reception of said sequential address signals. (d) a binary signal generator for providing a binary signal, (e) adding means having its inputs respectively connected to the binary signal generator and to the output of said first counter, adapted to add said address signals and the binary signal, to provide second address signals, (f) a second ROM, having digital representations of sequential elements of a substantially full cycle of a second predetermined signal waveform stored at sequential memory addresses, the number of signal element storage addresses being the same as in the first ROM, its address input being connected to the output of the adding means, and adapted to output said digital representations sequentially upon reception of said sequential second address signals, whereby the read out first predetermined signal and the read out second predetermined signal have a phase relationship dependent on the value of the binary signal.

Claim 8

A variable phase lock control comprising: (a) a first oscillator, (b) a first counter connected to the output of the oscillator for counting output pulses from said oscillator and generating sequential first address signals corresponding to the number of said pulses counted, including means for resetting said counter after a predetermined number of pulses, (c) a first ROM, having digital representations of sequential elements of a substantially full cycle of a first predetermined signal waveform stored at sequential memory addresses, its address input being connected to the output of the first counter and adapted to output said digital representations sequentially upon reception of said sequential address signals. (d) a binary signal generator for providing a binary signal, (e) adding means having its inputs respectively connected to the binary signal generator and to the output of said first counter, adapted to add said address signals and the binary signal, to provide second address signals, (f) a second ROM, having digital representations of sequential elements of a substantially full cycle of a second predetermined signal waveform stored at sequential memory addresses, the number of signal element storage addresses being the same as in the first ROM, its address input being connected to the output of the adding means, and adapted to output said digital representations sequentially upon reception of said sequential second address signals, whereby the read out first predetermined signal and the read out second predetermined signal have a phase relationship dependent on the value of the binary signal.

Claim 9

A variable phase lock control as defined in claim 6, in which the stored first predetermined signal waveform and the stored second predetermined signal waveform are the same.

Claim 10

A variable phase lock control as defined in claim 7 in which said first and second signals are sine waveforms.

Claim 11

A variable phase lock control as defined in claim 6, in which the stored first predetermined signal waveform and the stored second predetermined signal waveform are different.

Claim 12

A variable phase lock control as defined in claim 6, 7 or 9 in which the frequency of the oscillator is variable, whereby the output frequency of said first and second predetermined signals can be controlled, and said binary signal generator includes means for selecting said binary signal between zero and a number corresponding to the number of signal element storage addresses in one of said ROMs.

Claim 13

A variable phase lock control as defined in claim 6, 7 or 9 in which the frequency of the oscillator is variable, whereby the output frequency of said first and second predetermined signals can be controlled and further including a digital to analog converter connected to the output of each ROM for converting the output of said digital representations to analog waveforms, and low pass filter means connected to the output of each said converter for removing ripple remaining in said analog waveforms.

Claim 14

A variable phase lock control as defined in claim 6, 7 or 9 in which the frequency of the oscillator is variable, whereby the output frequency of said first and second predetermined signals can be controlled, said binary signal generator including a control calibrated from 0° to 360° having a decimal digital signal output proportioning the number of address locations storing said elements of said signal among 360 evenly divided parts, the control being adapted to output said decimal digital signal to a decimal to binary converter, the output of said decimal to binary converter being connected to said adding means.

Claim 15

A variable phase lock control comprising: (a) a first oscillator, (b) a first counter connected to the output of the oscillator for counting output pulses from said oscillator and generating sequential first address signals corresponding to the number of said pulses counted, including means for resetting said counter at a predetermined address, (c) a first ROM, having digital representations of sequential elements of a substantially full cycle of a first predetermined signal waveform stored at sequential memory addresses, its address input being connected to the output of the first counter and adapted to output said digital representations sequentially upon reception of said sequential address signals, (d) a binary signal generator for providing a binary signal, (e) a register for storing a digital representation of the binary signal, (f) a second counter, being connected to the output of the register and the output of the oscillator, for counting output pulses from said oscillator in sequence from the digital representation of the binary signal, to generate sequential second address signals corresponding to the number of pulses counted in addition to said digital representation of the binary signal, including means for resetting the counter at said predetermined address, (g) a second ROM, having digital representations of sequential elements of a substantially full cycle of a second predetermined signal waveform stored at sequential memory addresses, the number of signal element storage addresses being the same as in the first ROM, its address input being connected to the output of the second counter, and adapted to output said digital representations sequentially upon reception of said sequential second address signals, whereby the read out first predetermined signal and the read out second predetermined signal have a phase relationship dependent on the value of the binary signal.

Claim 16

A variable phase lock control comprising: (a) a first oscillator, (b) a first counter connected to the output of the oscillator for counting output pulses from said oscillator and generating sequential first address signals corresponding to the number of said pulses counted, including means for resetting said counter at a predetermined address, (c) a first ROM, having digital representations of sequential elements of a substantially full cycle of a first predetermined signal waveform stored at sequential memory addresses, its address input being connected to the output of the first counter and adapted to output said digital representations sequentially upon reception of said sequential address signals, (d) a binary signal generator for providing a binary signal, (e) a register for storing a digital representation of the binary signal, (f) a second counter, being connected to the output of the register and the output of the oscillator, for counting output pulses from said oscillator in sequence from the digital representation of the binary signal, to generate sequential second address signals corresponding to the number of pulses counted in addition to said digital representation of the binary signal, including means for resetting the counter at said predetermined address, (g) a second ROM, having digital representations of sequential elements of a substantially full cycle of a second predetermined signal waveform stored at sequential memory addresses, the number of signal element storage addresses being the same as in the first ROM, its address input being connected to the output of the second counter, and adapted to output said digital representations sequentially upon reception of said sequential second address signals, whereby the read out first predetermined signal and the read out second predetermined signal have a phase relationship dependent on the value of the binary signal.

Claim 17

A variable phase lock control as defined in claim 13, in which the stored first predetermined signal waveform and the stored second predetermined signal waveform are the same.

Claim 18

A variable phase lock control as defined in claim 14 in which said first and second signals are sine waveforms.

Claim 19

A variable phase lock control as defined in claim 13, in which the stored first predetermined signal waveform and the stored second predetermined signal waveform are different.

Claim 20

A variable phase lock control as defined in claim 13, 14 or 16 in which the frequency of the oscillator is variable, whereby the output frequency of said first and second predetermined signals can be controlled, and said binary signal generator includes means for selecting said binary signal between zero and a number corresponding to the number of signal element storage addresses in one of said ROMs.

Claim 21

A variable phase lock control as defined in claim 13, 14 or 16 in which the frequency of the oscillator is variable, whereby the output frequency of said first and second predetermined signals can be controlled, and further including a digital to analog converter connected to the output of each ROM for converting the output of said digital representations to analog waveforms, and low pass filter means connected to the output of each said converter for removing ripple remaining in said analog waveforms.

Claim 22

A variable phase lock control as defined in claim 13, 14 or 16 in which the frequency of the oscillator is variable, whereby the output frequency of said first and second predetermined signals can be controlled, said binary signal generator including a control calibrated from 0° to 360° having a decimal digital signal output proportioning the number of address locations storing said elements of said signal among 360 evenly divided parts, the control being adapted to output said decimal digital signal to a decimal to binary converter, the output of said decimal to binary converter being connected to said adding means.

Claim 25

A method of generating a pair of phase locked signals as defined in claim 20, further including the further step of converting the output signals of the memories to a pair of analog signals, and of filtering the analog signals to substantially remove ripple carried thereby.