US4441195A
Expired / Lapsed
US
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Short term response enhancement for digital phase-locked loop
Assignee: Bull HN Information Systems Inc
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Filing: 1981-07-10
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Granted: 1984-04-03
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Expires: 2001-07-10
Abstract
Abstract A short term response enhancement for a digital phase-locked loop is implemented to provide a relatively major change in the phase of the output signal over a relatively short period of time. The basic digital phase-locked loop determines the average number of pulses from a clock source which occur or are expected to occur between successive occurrences of the input signal to the digital phase-locked loop, and compares the number of pulses counted from the occurrence of the last output signal with the average number of pulses expected to occur, producing an output signal when the two numbers agree. The number of pulses which occur between successive cycles of the input signal are also compared against the previously determined average. A count which differs from the average count indicates a change in phase of the input signal. The present invention takes the absolute value of the measured error and, based upon the prior modification made during the previous two cycles of the input signal to the count sequence modifies the count sequence of the counter which is counting the number of pulses from the last output signal, by either adding one or subtracting one from the count sequence, thereby effecting a relatively major change in the phase of the output signal over a relatively short period of time.
Inventors
- 👤 David R. Baldwin
- 👤 Nicholas S. Lemak
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 06:56
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/099; H03L7/0991; H03L7/0994
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
393 words
In a phase-locked loop circuit with an enhancement circuit, for producing an output signal having a phase difference which is constant with respect to an input signal, said input signal having a time period subject to fluctuations, said phase-locked loop circuit including a timing element for generating clock pulses, a register element for storing a total number of said clock pulses which occur in a predetermined number of time periods of said input signal to generate a first and a second output signal, said first output signal representative of the average number of said clock pulses which occur in a time period over said predetermined number of time periods of said input signal, and said second output signal representative of a predicted number of said clock pulses which are expected to occur between said output signal and said input signal, a counter element operatively connected to said timing element for counting said clock pulses whereby said counter element contains a value of counter clock pulses, a compare element operatively connected to said counter element and further operatively connected to said register element, for comparing the value of counted clock pulses to said first output signal to generate said output signal, said output signal operatively coupled to said counter element for resetting said counter element, and a subtractor element operatively coupled to the output terminal of said counter element and further operatively coupled to said register element, for generating a difference signal between the value of counted clock pulses and said second output signal in response to said input signal, said difference signal operatively coupled to said register element, wherein said enhancement circuit comprises: (a) first means, having an input terminal adapted to receive an error signal, the input terminal of said first means operatively connected to said register element and to said subtractor element, for generating a numeric absolute value of said error signal and an algebraic sign of said error signal; and (b) logic means, having an input terminal adapted to receive the numeric absolute value of said error signal and the algebraic sign of said error signal, for generating a first signal and a second signal, said first and second signal being operatively coupled to said counter element, wherein the value of the counted clock pulses contained in said counter element is modified in response to said first and second signal.
Claim 2
Dependent Claim
393 words
In a phase-locked loop circuit with an enhancement circuit, for producing an output signal having a phase difference which is constant with respect to an input signal, said input signal having a time period subject to fluctuations, said phase-locked loop circuit including a timing element for generating clock pulses, a register element for storing a total number of said clock pulses which occur in a predetermined number of time periods of said input signal to generate a first and a second output signal, said first output signal representative of the average number of said clock pulses which occur in a time period over said predetermined number of time periods of said input signal, and said second output signal representative of a predicted number of said clock pulses which are expected to occur between said output signal and said input signal, a counter element operatively connected to said timing element for counting said clock pulses whereby said counter element contains a value of counter clock pulses, a compare element operatively connected to said counter element and further operatively connected to said register element, for comparing the value of counted clock pulses to said first output signal to generate said output signal, said output signal operatively coupled to said counter element for resetting said counter element, and a subtractor element operatively coupled to the output terminal of said counter element and further operatively coupled to said register element, for generating a difference signal between the value of counted clock pulses and said second output signal in response to said input signal, said difference signal operatively coupled to said register element, wherein said enhancement circuit comprises: (a) first means, having an input terminal adapted to receive an error signal, the input terminal of said first means operatively connected to said register element and to said subtractor element, for generating a numeric absolute value of said error signal and an algebraic sign of said error signal; and (b) logic means, having an input terminal adapted to receive the numeric absolute value of said error signal and the algebraic sign of said error signal, for generating a first signal and a second signal, said first and second signal being operatively coupled to said counter element, wherein the value of the counted clock pulses contained in said counter element is modified in response to said first and second signal.
Claim 3
Dependent Claim
48 words
In a phase-locked loop circuit according to claim 1, wherein said logic means comprises: (a) a plurality of gate means for implementing a predetermined set of conditions to generate said first and second signal; and (b) means for storing information representative of at least one of said conditions.
References Cited (Backward Citations)
US4242639A
Cited
US4375694A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-04-03 | 1987-10-03 | 1988-04-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-04-03 | 1991-10-03 | 1992-04-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-04-03 | 1995-10-03 | 1996-04-03 | $7700.00 | Window Closed / Lapsed |