US4439813A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Thin film discrete decoupling capacitor
Assignee: International Business Machines Corp
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Filing: 1981-07-21
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Granted: 1984-03-27
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Expires: 2001-07-21
Abstract
Abstract A decoupling capacitor for mounting on an integrated circuit multi-layer ceramic. A bottom layer electrode, is evaporated or sputtered onto a carrier. A high dielectric layer is deposited followed by the upper metallurgy and a top isolating layer. Via holes are etched to respective electrode layers, BLM deposited thereon followed by solder balls. The electrode is mounted onto the substrate, solder balls face down in contact with a compatible footprint.
Inventors
- 👤 William E. Dougherty
- 👤 Irving Feinberg
- 👤 James N. Humenik
- 👤 Alan Platt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 03:08
CPC Classifications
H; H01; H01G; H01G4/00; H01G4/002; H01G4/228; H01G2/00; H01G2/02; H01G2/06; H01G2/065; Y; Y10; Y10T; Y10T29/00; Y10T29/43; Y10T29/435
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
113 words
A chip capacitor comprising: a bottom conductive layer having sequentially coated thereon a dielectric layer, a top conductive layer, and an insulating layer; first and second via holes, wherein: said first via holes extend through said insulating layer to expose said top conductive layer, and said second via holes extend through said insulating, top conductive, and dielectric layers to expose said bottom conductive layer with said insulating layer extending about the side walls of said top conductor layer in said second via holes to insulate said top conductive layer; and isolated solder mounds selectively deposited on said insulating layer over and in via holes in electric contact with an exposed conductive layer therein.
Claim 2
Dependent Claim
113 words
A chip capacitor comprising: a bottom conductive layer having sequentially coated thereon a dielectric layer, a top conductive layer, and an insulating layer; first and second via holes, wherein: said first via holes extend through said insulating layer to expose said top conductive layer, and said second via holes extend through said insulating, top conductive, and dielectric layers to expose said bottom conductive layer with said insulating layer extending about the side walls of said top conductor layer in said second via holes to insulate said top conductive layer; and isolated solder mounds selectively deposited on said insulating layer over and in via holes in electric contact with an exposed conductive layer therein.
Claim 3
Dependent Claim
17 words
The chip capacitor of claim 1 further comprising a carrier substrate for mounting said bottom conductive layer.
Claim 4
Dependent Claim
11 words
The chip capacitor of claim 2, wherein said carrier is silicon.
Claim 5
Dependent Claim
20 words
The chip capacitor of claims 1 or 2, wherein said capacitor is mounted on a support surface for semiconductor chips.
Claim 6
Dependent Claim
21 words
The capacitor of claim 1 further comprising contact promoting metallurgy between each joined solder mound and an exposed conductive layer portion.
Claim 7
Dependent Claim
41 words
The capacitor of claim 5, wherein said bottom conductive layer comprises Ti/W or Ta; said dielectric layer comprises lead lanthanum zirconate titanate (PLZT), said top conductive layer comprises Al or Cu, and said insulating layer comprises quartz or SiO 2 .
Claim 8
Dependent Claim
19 words
The capacitor of claim 1, wherein said chip is solder bonded to circuit containing a support or ceramic substrate.
Claim 9
Dependent Claim
20 words
The structure of claim 7, wherein said support structure is a multilayered ceramic having a conductive wiring pattern embedded therein.
Claim 10
Independent Claim
112 words
A method of making a discrete thin film capacitor comprising the steps of: successively depositing a bottom conductive layer, a dielectric layer and a top conductive layer on an area of a carrier substrate, etching a portion of said top conductive layer and said dielectric layer to expose said bottom conductive layer, depositing a layer of insulating material over said etched portion and unetched areas, etching said insulating material to expose said top conductive layer at selected portions of said unetched area and to isolate said top conductive layer from said bottom conductive layer while exposing said bottom conductive layer, and depositing a layer of ball limiting metallurgy over all exposed portions.
Claim 11
Independent Claim
112 words
A method of making a discrete thin film capacitor comprising the steps of: successively depositing a bottom conductive layer, a dielectric layer and a top conductive layer on an area of a carrier substrate, etching a portion of said top conductive layer and said dielectric layer to expose said bottom conductive layer, depositing a layer of insulating material over said etched portion and unetched areas, etching said insulating material to expose said top conductive layer at selected portions of said unetched area and to isolate said top conductive layer from said bottom conductive layer while exposing said bottom conductive layer, and depositing a layer of ball limiting metallurgy over all exposed portions.
Claim 12
Dependent Claim
38 words
The method of claim 9, wherein the step of depositing a bottom layer and a dielectric layer comprises sputtering or evaporating said bottom layer directly on said carrier and sputtering said dielectric layer directly on said bottom layer.
Claim 13
Dependent Claim
32 words
The method of claim 10, further comprising the step of evaporating a metal selected from the group consisting of Al or Cu directly onto the dielectric layer to form said top layer.
Claim 14
Dependent Claim
47 words
The method of claim 9, further comprising the steps of placing a solder ball over selected layers of said ball limiting metallurgy to define elective contacts with said top and bottom conductive layers and, cutting the resulting capacitor to size for mounting on an integrated circuit laminate.
Claim 15
Dependent Claim
11 words
The method of claim 9 wherein said insulating material is quartz.
References Cited (Backward Citations)
US3021589A
Cited
US3278815A
Cited
US3292240A
Cited
US3303393A
Cited
US3638085A
Cited
US3897074A
Cited
US4071878A
Cited
US4104697A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-03-27 | 1987-09-26 | 1988-03-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-03-27 | 1991-09-26 | 1992-03-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-03-27 | 1995-09-26 | 1996-03-27 | $7700.00 | Window Closed / Lapsed |