US4439697A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Sense amplifier circuit
Assignee: Toshiba Corp
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Filing: 1981-12-22
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Granted: 1984-03-27
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Expires: 2001-12-22
Abstract
Abstract A sense amplifier circuit is disclosed in which a ROM is grouped into a plurality of ROM arrays and outputs from sense amplifiers provided for each ROM array are supplied to a single output terminal. In the sense amplifier circuit, each sense amplifier has a P-MOS FET connected between the output of the ROM array and a ground terminal and connected at the gate to a preset terminal, P-MOS FETs connected between the output of the ROM array and a positive power source and whose gates are respectively connected to the output terminal and a preset terminal, and an N MOS FET connected between the output terminal and the ground terminal and at the gate to the output terminal of the ROM array. Further, a P MOS FET is connected between the output terminal and the power source terminal and at the gate to an inverted preset terminal.
Inventors
- 👤 Yasoji Suzuki
- 👤 Hiroaki Suzuki
- 👤 Yukihiro Saeki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 13:38
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/08; G11C17/10; G11C17/12
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
253 words
A sense amplifier circuit which is used for a plurality of read only memory arrays each having a single output terminal in a complementally metal-oxide-semiconductor integrated circuit, and has a plurality of input terminals respectively connected to the output terminals of said read only memory arrays and a single output terminal, said sense amplifier circuit comprising: first and second power source terminals; first and second clock terminals supplied with complementary signals; a plurality of first transistors of a first channel type each connected between said first power source terminal and a corresponding one of said input terminals and each having a control terminal connected to said first clock terminal; a plurality of second transistors of a second channel type each connected between said second power source terminal and a corresponding one of said input terminals and each having a control terminal connected to said output terminal; a plurality of third transistors of the first channel type connected between said output terminal and said first power source terminal and each having a control terminal connected to a corresponding one of said input terminals; a plurality of fourth transistors connected between said first and second power source terminals through a corresponding one of said second and third transistors and each having a control terminal connected to either of said first and second clock terminals; and a fifth transistor of the second channel type connected between said output terminal and said second power source terminal and having a control terminal connected to said second clock terminal.
Claim 2
Dependent Claim
253 words
A sense amplifier circuit which is used for a plurality of read only memory arrays each having a single output terminal in a complementally metal-oxide-semiconductor integrated circuit, and has a plurality of input terminals respectively connected to the output terminals of said read only memory arrays and a single output terminal, said sense amplifier circuit comprising: first and second power source terminals; first and second clock terminals supplied with complementary signals; a plurality of first transistors of a first channel type each connected between said first power source terminal and a corresponding one of said input terminals and each having a control terminal connected to said first clock terminal; a plurality of second transistors of a second channel type each connected between said second power source terminal and a corresponding one of said input terminals and each having a control terminal connected to said output terminal; a plurality of third transistors of the first channel type connected between said output terminal and said first power source terminal and each having a control terminal connected to a corresponding one of said input terminals; a plurality of fourth transistors connected between said first and second power source terminals through a corresponding one of said second and third transistors and each having a control terminal connected to either of said first and second clock terminals; and a fifth transistor of the second channel type connected between said output terminal and said second power source terminal and having a control terminal connected to said second clock terminal.
Claim 3
Dependent Claim
27 words
A sense amplifier circuit according to claim 1, in which said third transistors are connected in parallel between said output terminal and said first power source terminal.
Claim 4
Dependent Claim
48 words
A sense amplifier circuit according to claim 2, in which said fourth transistors are each comprised of a transistor of the second channel type which is connected between said second transistor and said second power source terminal and having a control terminal connected to said first clock terminal.
Claim 5
Dependent Claim
46 words
A sense amplifier circuit according to claim 2, in which said fourth transistors are each comprised of a transistor of the first channel type connected between said third transistor and said first power source terminal and having a control terminal connected to said second clock terminal.
Claim 6
Dependent Claim
45 words
A sense amplifier circuit according to claim 1, in which said third transistors are connected in series between said first and second power source terminals and one of the connection points in the series circuit of said third transistors is connected to said output terminal.
Claim 7
Dependent Claim
46 words
A sense amplifier circuit according to claim 5, in which said fourth transistors are each comprised of a transistor of the second channel type connected between said second transistor and said second power source terminal and having a control terminal connected to said first clock terminal.
Claim 8
Dependent Claim
50 words
A sense amplifier circuit according to claim 5, in which said fourth transistors are each comprised of a transistor of the first channel type connected between said series circuit of said third transistors and said first power source terminal and having a control terminal connected to said second clock terminal.
Claim 9
Dependent Claim
85 words
A sense amplifier circuit according to one of claims 3, 4, 6 and 7, in which said first and second power source terminals are ground and positive terminals, respectively, said first clock terminal is supplied with a logic 1 signal in a precharge mode and a logic 0 signal in other modes, said transistors of the first channel type are N channel metal oxide semiconductor field effect transistors and said transistors of the second channel type are P channel metal oxide semiconductor field effect transistors.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-03-27 | 1987-09-26 | 1988-03-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-03-27 | 1991-09-26 | 1992-03-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-03-27 | 1995-09-26 | 1996-03-27 | $7700.00 | Window Closed / Lapsed |