US4439637A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Low loop current switch latch circuit
Assignee: STMicroelectronics lnc USA
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Filing: 1981-12-28
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Granted: 1984-03-27
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Expires: 2001-12-28
Abstract
Abstract A low loop current switch latch circuit (10) monitors a residual current which is derived from a telephone line and is proportional to the current drawn by a telephone subscriber circuit. Bipolar transistors (20, 26) are connected to produce a proportional current to the residual current. A current mirror circuit includes a master transistor (30) and a slave transistor (32). The proportional current is drawn through the master transistor (30). The current produced by the slave transistor (32) is provided to a node (33). A constant power source (36) provides a constant current to a node (39). A pair of cross-coupled transistors (40, 46) are connected to the nodes (33, 39) such that the cross-coupled transistors are set to first and second states as a function of the current derived from the slave transistor (32). A bias current transistor (52) is activated by the cross-coupled transistors (40, 46) to draw a preset biased current from an amplifier (60), thereby changing the amplifier from a first gain to a second gain condition. The circuit (10) therefor sets the gain of the amplifier (60) through switching action utilizing hysteresis, the switching being a function of the amplitude of the residual current passed through the transistor (20).
Inventors
- 👤 Michael B. Terry
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 20:24
CPC Classifications
H; H04; H04M; H04M1/00; H04M1/738; H04M1/76
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
97 words
A switch latch circuit for controlling a bias current of an amplifier in a telephone subscriber's device powered by the telephone lines, comprising: means for monitoring a residual current to produce a control current proportional to said residual current; cross-coupled transistor means connected to receive said control current and switch with hysteresis between a first state and a second state as a function of said control current, and means coupled to said cross-coupled transistor means for drawing a predetermined bias current from said amplifier when said cross-coupled transistor means is in a selected one of said states.
Claim 2
Dependent Claim
97 words
A switch latch circuit for controlling a bias current of an amplifier in a telephone subscriber's device powered by the telephone lines, comprising: means for monitoring a residual current to produce a control current proportional to said residual current; cross-coupled transistor means connected to receive said control current and switch with hysteresis between a first state and a second state as a function of said control current, and means coupled to said cross-coupled transistor means for drawing a predetermined bias current from said amplifier when said cross-coupled transistor means is in a selected one of said states.
Claim 3
Dependent Claim
176 words
The switch latch circuit recited in claim 1 wherein said means for monitoring a residual current to produce a control current comprises: a bipolar first transistor which passes said residual current through the emitter and collector terminals thereof and has the collector terminal thereof connected to a first power terminal; a bipolar second transistor having the base terminal thereof connected to the base terminal of said first bipolar transistor; a first resistor connected between the emitter terminal of said first transistor and a second power terminal; and a current mirror circuit including a master bipolar third transistor having the base and collector terminals thereof connected to the collector terminal of said second transistor and having the emitter terminal thereof connected to a third power terminal, said current mirror circuit further including a slave bipolar fourth transistor having the base terminal thereof connected to the base terminal of said third transistor, the emitter terminal thereof connected to said third power terminal wherein said control current is passed between the collector and emitter terminals of said fourth transistor.
Claim 4
Dependent Claim
127 words
The switch latch circuit recited in claim 1 wherein said cross-coupled transistor means comprises: a first resistor having a first terminal connected to receive said control current; a first bipolar transistor having the collector terminal thereof connected to a second terminal of said first resistor and the emitter terminal thereof connected to a first power terminal; a second bipolar transistor having the base terminal thereof connected to the first terminal of said first resistor and the emitter terminal thereof connected to said first power terminal; a second resistor connected between the base terminal of said first transistor and the collector terminal of said second transistor; and a current source for providing a constant current from a second power terminal to the collector terminal of said second transistor.
Claim 5
Dependent Claim
85 words
The switch latch circuit recited in claim 1 wherein said means for drawing a predetermined bias current comprises: a resistor having a first terminal thereof connected to a node of said cross-coupled transistor means, said node driven to first and second voltage states; and a bipolar transistor having the base terminal thereof connected to a second terminal of said resistor having the emitter terminal thereof connected to a power terminal and having the collector terminal thereof connected to draw a bias current from said amplifier.
Claim 6
Dependent Claim
340 words
A switch latch circuit for controlling a bias current of an amplifier in response to a residual current divided from a telephone line, the switch latch circuit comprising: a first transistor having the collector terminal thereof connected to a first power terminal and passing said residual current through the collector and emitter terminals thereof; a second transistor having the base terminal thereof connected to the base terminal of said first transistor; a first resistor connected between the emitter terminal of said second transistor and a second power terminal; a first current mirror circuit including a master third transistor having the emitter terminal thereof connected to a third power terminal and the base and collector terminals thereof connected to the collector terminal of said second transistor and including a slave fourth transistor having the emitter terminal thereof connected to said third power terminal and the base terminal thereof connected to the base terminal of said third transistor; a second resistor having a first terminal thereof connected to the collector terminal of said fourth transistor; a fifth transistor having the collector terminal thereof connected to a second terminal of said second resistor and the emitter terminal thereof connected to said second power terminal; a sixth transistor having the base terminal thereof connected to the first terminal of said second resistor and the emitter terminal thereof connected to said second power terminal; a third resistor connected between the collector terminal of said sixth transistor and the base terminal of said fifth transistor; a current source for providing a constant current from said third power terminal to the collector terminal of said sixth transistor; a fourth resistor having a first terminal connected to the collector terminal of said sixth transistor; and a seventh transistor having the base terminal thereof connected to a second terminal of said fourth resistor, having the emitter terminal thereof connected to said second power terminal and having the collector terminal thereof connected to said amplifier for drawing said bias current therefrom in response to the amplitude of said residual current.
Claim 7
Dependent Claim
340 words
A switch latch circuit for controlling a bias current of an amplifier in response to a residual current divided from a telephone line, the switch latch circuit comprising: a first transistor having the collector terminal thereof connected to a first power terminal and passing said residual current through the collector and emitter terminals thereof; a second transistor having the base terminal thereof connected to the base terminal of said first transistor; a first resistor connected between the emitter terminal of said second transistor and a second power terminal; a first current mirror circuit including a master third transistor having the emitter terminal thereof connected to a third power terminal and the base and collector terminals thereof connected to the collector terminal of said second transistor and including a slave fourth transistor having the emitter terminal thereof connected to said third power terminal and the base terminal thereof connected to the base terminal of said third transistor; a second resistor having a first terminal thereof connected to the collector terminal of said fourth transistor; a fifth transistor having the collector terminal thereof connected to a second terminal of said second resistor and the emitter terminal thereof connected to said second power terminal; a sixth transistor having the base terminal thereof connected to the first terminal of said second resistor and the emitter terminal thereof connected to said second power terminal; a third resistor connected between the collector terminal of said sixth transistor and the base terminal of said fifth transistor; a current source for providing a constant current from said third power terminal to the collector terminal of said sixth transistor; a fourth resistor having a first terminal connected to the collector terminal of said sixth transistor; and a seventh transistor having the base terminal thereof connected to a second terminal of said fourth resistor, having the emitter terminal thereof connected to said second power terminal and having the collector terminal thereof connected to said amplifier for drawing said bias current therefrom in response to the amplitude of said residual current.
References Cited (Backward Citations)
US3781481A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-03-27 | 1987-09-26 | 1988-03-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-03-27 | 1991-09-26 | 1992-03-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-03-27 | 1995-09-26 | 1996-03-27 | $7700.00 | Window Closed / Lapsed |