US4437148A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Peak voltage clamped power supply
Assignee: AT&T Inc
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Filing: 1981-12-09
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Granted: 1984-03-13
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Expires: 2001-12-09
Abstract
Abstract The cost and energy efficiency of a power supply are optimized in a semi-regulated circuit wherein regulation occurs only under a high voltage, low current condition when peak output voltage would otherwise exceed a maximum specified voltage. The circuit includes a full wave rectifier (21-24) driving a modified pi filter (33-35). A transistor (62) in series with the filter is biased by a resistor (65) to normally operate in a fully saturated, low power dissipating mode. When the output (31-32) voltage approaches the specified maximum, the breakdown voltage of a zener diode (71) is exceeded, and the output voltage is clamped to the specified maximum through the zener diode and the base-emitter junction of the transistor.
Inventors
- 👤 Gabriel G. Suranyi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 09:49
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/18; G05F1/00; G05F1/10; G05F1/46; G05F1/56; G05F1/575
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
193 words
A circuit for efficiently stabilizing and limiting a direct current voltage at an output thereof comprising: means for supplying a first full wave rectified voltage; filter means for stabilizing and reducing the ripple of the first full wave rectified voltage; a transistor having a collector terminal and an emitter terminal coupled in series with the filter means; means, coupled to the transistor, for biasing the transistor to function in a lower power dissipating saturated mode over a greater portion of the expected operating range of the circuit when the output voltage of the circuit is less than a predetermined maximum and for biasing the transistor to function in a higher power dissipating unsaturated mode over a lesser portion of said range when the output voltage of the circuit is substantially equal to the predetermined maximum; and means for supplying a second full wave rectified voltage having a peak value different from the peak value of the first full wave rectified voltage; and wherein the biasing means includes a zener diode coupled to a base terminal of the transistor and, in series through a biasing impedance element, to the second full wave rectified voltage.
Claim 2
Dependent Claim
193 words
A circuit for efficiently stabilizing and limiting a direct current voltage at an output thereof comprising: means for supplying a first full wave rectified voltage; filter means for stabilizing and reducing the ripple of the first full wave rectified voltage; a transistor having a collector terminal and an emitter terminal coupled in series with the filter means; means, coupled to the transistor, for biasing the transistor to function in a lower power dissipating saturated mode over a greater portion of the expected operating range of the circuit when the output voltage of the circuit is less than a predetermined maximum and for biasing the transistor to function in a higher power dissipating unsaturated mode over a lesser portion of said range when the output voltage of the circuit is substantially equal to the predetermined maximum; and means for supplying a second full wave rectified voltage having a peak value different from the peak value of the first full wave rectified voltage; and wherein the biasing means includes a zener diode coupled to a base terminal of the transistor and, in series through a biasing impedance element, to the second full wave rectified voltage.
Claim 3
Dependent Claim
37 words
A circuit as recited in claim 1 further comprising a capacitor coupled in parallel with the series combination of the zener diode and the impedance element for smoothing the ripple of the second full wave rectified voltage.
Claim 4
Dependent Claim
50 words
A circuit as recited in claim 2, wherein: the filter is a pi filter having a pair of capacitors coupled in parallel with the output and an inductor coupled in series with the output; and the collector and emitter terminals of the transistor are coupled in series with the inductor.
Claim 5
Dependent Claim
18 words
A circuit as recited in claim 3 further comprising a bleeder resistor coupled in parallel with the output.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-03-13 | 1987-09-12 | 1988-03-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-03-13 | 1991-09-12 | 1992-03-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-03-13 | 1995-09-12 | 1996-03-13 | $7700.00 | Window Closed / Lapsed |