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US4437069A Expired / Lapsed US ⏱️ 0.0 years remaining

Low noise tuned amplifier

Assignee: National Aeronautics and Space Administration
•
Filing: 1981-06-12
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Granted: 1984-03-13
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Expires: 2001-06-12
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Abstract

Abstract A bandpass amplifier employing a field effect transistor amplifier first stage (10) with a resistive load (R 2 ) either a.c. or directly coupled to the non-inverting input of an operational amplifier second stage (20) which is loaded in a Wien Bridge configuration. The bandpass amplifier may be operated with a signal injected into the gate terminal (G) of the field effect transistor and the signal output taken from the output terminal of the operational amplifier. The operational amplifier stage appears as an inductive reactance, capacitive reactance and negative resistance at the non-inverting input of the operational amplifier, all of which appear in parallel with the resistive load (R 2 ) of the field effect transistor.

Inventors

  • 👤 Leonard L. Kleinberg

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 17:34
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/42; H03F1/48; H03F1/483; H03F3/00; H03F3/181; H03F3/183; H03F3/185; H03F3/1855; H03F2200/00; H03F2200/261; H03F2200/372

Claims Analysis

Total Claims: 11
Claim 1
Independent Claim 92 words
A tuned, low noise amplifier comprising: a first amplifying stage including a field effect transistor with gate, drain and source connections and having both signal input and signal output means; a second amplifying stage driven by said first amplifying stage from said first stage signal output means and including an operational amplifier having inverting and non-inverting inputs and a second stage signal output means, said operational amplifier being loaded in a reactive impedance bridge configuration and said second stage reflecting a negative resistance in parallel with said first stage signal output means.
Claim 2
Dependent Claim 92 words
A tuned, low noise amplifier comprising: a first amplifying stage including a field effect transistor with gate, drain and source connections and having both signal input and signal output means; a second amplifying stage driven by said first amplifying stage from said first stage signal output means and including an operational amplifier having inverting and non-inverting inputs and a second stage signal output means, said operational amplifier being loaded in a reactive impedance bridge configuration and said second stage reflecting a negative resistance in parallel with said first stage signal output means.
Claim 3
Dependent Claim 13 words
The amplifier of claim 1 wherein said bridge configuration is a Wien Bridge.
Claim 4
Dependent Claim 92 words
The amplifier of claim 2 wherein said Wien Bridge configuration load comprises a first resistance (R 4 ) connected between said second stage signal output means and said inverting input, a second resistance (R 5 , R 6 ) network connected between said inverting input and ground, a shunt capacitance (C 5 )--third resistance (R 9 ) network connected between said non-inverting input and ground and a series capacitance (C 14 )--fourth resistance (R 7 , R 8 ) network connected between said second stage signal output means and said non-inverting input.
Claim 5
Dependent Claim 29 words
The amplifier of claim 3 wherein the value of said first resistance (R 4 ) approaches twice the value of said second resistance (R 5 , R 6 ).
Claim 6
Dependent Claim 22 words
The amplifier of claim 3 wherein said field effect transistor has a resistance load (R 2 ) connected to said drain connection.
Claim 7
Dependent Claim 33 words
The amplifier of claim 5 wherein said field effect resistance load at said drain connection (R 2 ) is approximately equal in magnitude to said fourth resistance (R 7 , R 8 ).
Claim 8
Dependent Claim 24 words
The amplifier of claim 3 wherein said shunt capacitance (C 5 ) is approximately equal in value to said series capacitance (C 4 ).
Claim 9
Dependent Claim 19 words
The amplifier of claim 1 wherein said first stage signal output means is a resistive load (R 2 ).
Claim 10
Dependent Claim 17 words
The amplifier of claim 8 wherein said negative resistance is larger in magnitude than said resistive load.
Claim 11
Dependent Claim 21 words
The amplifier of claim 1 wherein said first stage drives said second stage at said non-inverting input of said operational amplifier.

References Cited (Backward Citations)

US3405368A Cited
US3597696A Cited
US3967209A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1987-03-13 1987-09-12 1988-03-13 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1991-03-13 1991-09-12 1992-03-13 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1995-03-13 1995-09-12 1996-03-13 $7700.00 Window Closed / Lapsed

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