US4435789A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit for a read-only memory organized in rows and columns to prevent bit line potentials from dropping
Assignee: Siemens AG
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Filing: 1981-08-06
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Granted: 1984-03-06
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Expires: 2001-08-06
Abstract
Abstract Circuit arrangement for a read-only memory organized in rows and columns, including bit lines having potentials applied thereto, and selection circuits being connected to the bit lines, being addressed by a bit line decoder and containing at least one selection transistor having a cut-off voltage and a gate potential, for preventing bit line potentials from dropping below a given value at which the selection circuits become conducting without having been selected by the bit line decoder, including current-feed lines each being connected to a different one of the bit lines for feeding current to the bit lines and for ensuring that for each of the selection circuits not selected by the bit line decoder the difference between at least one gate potential of the participating selection transistors and the respective bit line potential is smaller than the cut-off voltage of the respective selection transistors.
Inventors
- 👤 Burkhard Giebel
- 👤 Hans Moormann
- 👤 Lothar Schrader
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 13:01
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/08; G11C17/10; G11C17/12
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
200 words
Circuit arrangement for a read-only memory organized in rows and columns, including bit lines having potentials applied thereto, and selection circuits being connected to the bit lines, being addressed by a bit line decoder and containing at least one selection transistor having a cut-off voltage and a gate potential, for preventing bit line potentials from dropping below a given value at which the selection circuits become conducting without having been selected by the bit line decoder, comprising current-feed lines each being connected to a different one of the bit lines for feeding current to the bit lines and for ensuring that for each of the selection circuits not selected by the bit line decoder the difference between at least one gate potential of the participating selection transistors and the respective bit line potential is smaller that the cut-off voltage of the respective section transistors, and including first and second potential sources, said current-feed lines each including an MOS transistor having a source-drain path connected between a different respective bit line and said first potential source and a gate connected to said second potential source, said potential sources being chosen so as to prevent current from flowing in non-selected selection circuits.
Claim 2
Dependent Claim
200 words
Circuit arrangement for a read-only memory organized in rows and columns, including bit lines having potentials applied thereto, and selection circuits being connected to the bit lines, being addressed by a bit line decoder and containing at least one selection transistor having a cut-off voltage and a gate potential, for preventing bit line potentials from dropping below a given value at which the selection circuits become conducting without having been selected by the bit line decoder, comprising current-feed lines each being connected to a different one of the bit lines for feeding current to the bit lines and for ensuring that for each of the selection circuits not selected by the bit line decoder the difference between at least one gate potential of the participating selection transistors and the respective bit line potential is smaller that the cut-off voltage of the respective section transistors, and including first and second potential sources, said current-feed lines each including an MOS transistor having a source-drain path connected between a different respective bit line and said first potential source and a gate connected to said second potential source, said potential sources being chosen so as to prevent current from flowing in non-selected selection circuits.
Claim 3
Dependent Claim
18 words
Circuit arrangement according to claim 1, wherein at least one of said potential sources are constant in time.
Claim 4
Dependent Claim
21 words
Circuit according to claim 1, including a supply potential source, said first potential source being equal to said supply potential source.
Claim 5
Dependent Claim
15 words
Circuit according to claim 1, wherein at least one of said potential sources is clock-controlled.
Claim 6
Dependent Claim
52 words
Circuit arrangement according to claim 1 or 4, wherein said MOS transistors of said current-feed lines are of the same type and have the same cut-off voltages as the selection transistors, and said second potential source is higher than the gate potential of at least one selection transistor of non-selected selection circuits.
Claim 7
Dependent Claim
79 words
Circuit arrangement according to claim 5, including a reference potential source, a supply potential source, and a voltage divider generating said second potential source at a tap thereof, said voltage divider including a first MOS transistor connected to said supply potential source as a load and a second MOS gate-drain-connected transistor connected to said reference potential source, said second transistor being of the same type and having substantially the same cut-off voltage as said transistors of said current-feed lines.
Claim 8
Dependent Claim
104 words
Circuit arrangement according to claim 5, wherein the read-only memory is switchable between a power-down operating mode and an active operating mode, including a reference potential source, a signal source indicating the power-down operating mode, a first MOS transistor being addressed by said power-down operating mode signal source, a second gate-drain-connected MOS transistor being connected to said reference potential source and being connected in series with said first transistor, said second transistor being of the same type and having substantially the same cut-off voltage as said transistors of said current-feed branches, and a junction point disposed between said transistors forming said second potential source.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-03-06 | 1987-09-05 | 1988-03-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-03-06 | 1991-09-05 | 1992-03-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-03-06 | 1995-09-05 | 1996-03-06 | $7700.00 | Window Closed / Lapsed |