US4435781A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory-based parallel data output controller
Assignee: National Aeronautics and Space Administration
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Filing: 1983-06-09
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Granted: 1984-03-06
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Expires: 2003-06-09
Abstract
Abstract A memory-based parallel data output controller employs associative memories and memory mapping to decommutate multiple channels of telemetry data. The output controller contains a random access memory (RAM) (10) which has at least as many address locations as there are channels. A word counter addresses the RAM (10) which provides as its outputs an encoded peripheral device number and a MSB/LSB-first flag. The encoded device number and a bit counter address a second RAM (20) which contains START and STOP flags to pick out the required bits from the specified word number. The LSB/MSB, START and STOP flags, along with the serial input digital data go to a control block (30) which selectively fills a shift register (40,42) used to drive the parallel data output bus (32). A strobe pulse is also generated which enables a decoder (34) to select the appropriate peripheral device using the encoded device number. A microcomputer connected to an address bus (16) can be used to set the contents of the RAMs via multiplexers (14,24) during the initialization phase using the technique of memory mapping.
Inventors
- 👤 Raymond J. Stattel
- 👤 James K. Niswander
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 22:22
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/04; H04J3/047
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
316 words
A memory-based parallel data output controller for the extraction of predetermined bits from an inputted bit serial digital data stream for use with a frame synchronizer of the type having a word counter, a bit counter, a link synchronization status signal and a reference clock, said output controller receiving said inputted bit serial digital data stream and decommutating said predetermined extracted bits into multiple channels of predetermined parallel telemetry data to a plurality of peripheral devices, comprising: a first random access memory having address lines and at least as many memory address locations as there are channels, said word counter being connected to said address lines of said first random access memory which provides as its output an encoded peripheral device number and a first flag denoting either most significant bit or least significant bit first operation, a second random access memory having address lines and for outputting second and third flags to pick out the start and stop of said predetermined extracted bits, said encoded peripheral device number output from said first random access memory and said bit counter being connected to the address lines of said second random access memory, a serial-in parallel-out shift register for outputting said predetermined extracted bits in a parallel format representing said parallel telemetry data, shift register control means for receiving said bit serial digital data stream, said first, second and third flags, said link synchronization status signal and said reference clock and, therefrom, for developing and outputting a strobe pulse, a mode pulse, a shift pulse, and serial data pulse stream all of which output pulses being inputted into said shift register, decoding means connected to receive said encoded peripheral device number output from said first random access memory and receiving and being enabled by said output strobe pulse for selecting one of said plurality of peripheral devices to receive said parallel telemetry data from said shift register.
Claim 2
Dependent Claim
316 words
A memory-based parallel data output controller for the extraction of predetermined bits from an inputted bit serial digital data stream for use with a frame synchronizer of the type having a word counter, a bit counter, a link synchronization status signal and a reference clock, said output controller receiving said inputted bit serial digital data stream and decommutating said predetermined extracted bits into multiple channels of predetermined parallel telemetry data to a plurality of peripheral devices, comprising: a first random access memory having address lines and at least as many memory address locations as there are channels, said word counter being connected to said address lines of said first random access memory which provides as its output an encoded peripheral device number and a first flag denoting either most significant bit or least significant bit first operation, a second random access memory having address lines and for outputting second and third flags to pick out the start and stop of said predetermined extracted bits, said encoded peripheral device number output from said first random access memory and said bit counter being connected to the address lines of said second random access memory, a serial-in parallel-out shift register for outputting said predetermined extracted bits in a parallel format representing said parallel telemetry data, shift register control means for receiving said bit serial digital data stream, said first, second and third flags, said link synchronization status signal and said reference clock and, therefrom, for developing and outputting a strobe pulse, a mode pulse, a shift pulse, and serial data pulse stream all of which output pulses being inputted into said shift register, decoding means connected to receive said encoded peripheral device number output from said first random access memory and receiving and being enabled by said output strobe pulse for selecting one of said plurality of peripheral devices to receive said parallel telemetry data from said shift register.
Claim 3
Dependent Claim
155 words
A memory-based parallel data output controller as recited in claim 1 further comprising: a first multiplexer having two sets of inputs, one set being connected to said word counter and the other set being connected to an address but accessible by a data processing device, the output of said first multiplexer being connected to the address lines of said first random access memory, and a second multiplexer having two sets of inputs, a part of one set being connected to said encoded peripheral device number output from said first random access memory and the remaining part being connected to said bit counter, the other set of inputs being connected to said address bus, the outputs of said second multiplexer being connected to the address lines of said second random access memory, said data processing device being used to set the contents of said first and second random access memories using the technique of memory mapping.
Claim 4
Dependent Claim
39 words
A memory-based parallel data output controller as recited in claim 2 further comprising means connected to said frame synchronizer for forcing the output of said parallel data output controller to zero in the event that frame synchronization is lost.
References Cited (Backward Citations)
US3742466A
Cited
US4016549A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-03-06 | 1987-09-05 | 1988-03-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-03-06 | 1991-09-05 | 1992-03-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-03-06 | 1995-09-05 | 1996-03-06 | $7700.00 | Window Closed / Lapsed |