US4435656A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Phase inverter circuit
Assignee: Mitsubishi Electric Corp
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Filing: 1982-03-22
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Granted: 1984-03-06
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Expires: 2002-03-22
Abstract
Abstract A phase-inverter circuit comprising two differential current gates each comprising three transistors, the emitters of which are separated from ground by a gate current source. The signal to be inverted is applied across the bases of first and second transistors in each gate. The inverting signal is cross-applied across bases of the third transistors. The gates have the bases of their first and second transistors cross-connected. The collectors of the third transistors are connected to V cc . The collectors of the first transistors are cross-connected to the output terminals, themselves separated from V cc by resistors. As a result, the number of elements cascaded between V cc and ground is reduced.
Inventors
- 👤 Yasuta Tomuro
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 04:58
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/086; H03K17/00; H03K17/51; H03K17/56; H03K17/60; H03K17/66; H03K17/661; H03K5/00; H03K5/01; H03K5/02
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
135 words
A phase inverter circuit, comprising: a first differential current gate including first, second and third active elements and a first constant current source; a second differential current gate including fourth, fifth and sixth active elements and a second constant current source; a first output terminal connected to the output terminals of said first and fourth active elements; a second output terminal connected to the output terminals of said second and fifth active elements; a first input terminal connected to the input terminals of said first and fifth active elements; and a second input terminal connected to the input terminals of said second and fourth active elements, an input signal being applied across said first and second input terminals, and a phase switching signal being applied across input terminals of said third and sixth active elements.
Claim 2
Dependent Claim
135 words
A phase inverter circuit, comprising: a first differential current gate including first, second and third active elements and a first constant current source; a second differential current gate including fourth, fifth and sixth active elements and a second constant current source; a first output terminal connected to the output terminals of said first and fourth active elements; a second output terminal connected to the output terminals of said second and fifth active elements; a first input terminal connected to the input terminals of said first and fifth active elements; and a second input terminal connected to the input terminals of said second and fourth active elements, an input signal being applied across said first and second input terminals, and a phase switching signal being applied across input terminals of said third and sixth active elements.
Claim 3
Dependent Claim
165 words
A phase inverter circuit comprising: a first differential current gate including first, second and third transistors and a first constant current source; a second differential current gate including fourth, fifth and sixth transistors and a second constant current source; a first output connecting part through which the collectors of said first and fourth transistors are electrically connected to one other; a second output connecting part through which the collectors of said second and fifth transistors are electrically connected to one other; a first input connecting part through which the bases of said first and fifth transistors are electrically connected to one other, a second input connecting part through which the bases of said second and fourth transistors are electrically connected to one other; input terminals, by means of which an input signal is applied across said first and second input connecting parts; and switching signal input terminals, by means of which a phase switching signal is applied across bases of said third and sixth transistors.
Claim 4
Dependent Claim
165 words
A phase inverter circuit comprising: a first differential current gate including first, second and third transistors and a first constant current source; a second differential current gate including fourth, fifth and sixth transistors and a second constant current source; a first output connecting part through which the collectors of said first and fourth transistors are electrically connected to one other; a second output connecting part through which the collectors of said second and fifth transistors are electrically connected to one other; a first input connecting part through which the bases of said first and fifth transistors are electrically connected to one other, a second input connecting part through which the bases of said second and fourth transistors are electrically connected to one other; input terminals, by means of which an input signal is applied across said first and second input connecting parts; and switching signal input terminals, by means of which a phase switching signal is applied across bases of said third and sixth transistors.
Claim 5
Dependent Claim
43 words
A phase inverter circuit as claimed in claim 2, wherein emitters of said first, second and third transistors are connected to said first constant current source, and emitters of said fourth, fifth and sixth transistors are connected to said second constant current source.
Claim 6
Dependent Claim
53 words
A phase inverter circuit as claimed in claim 3, wherein when a base voltage of said third and sixth transistors is larger by predetermined amount than base voltages of said first and second, and said fourth and fifth transistors, respectively, said first, second, fourth and fifth transistors are placed in a cut-off state.
Claim 7
Dependent Claim
52 words
A phase inverter circuit as claimed in claim 4, wherein when a base voltage of said third and sixth transistors is smaller by a predetermined amount than base voltages of said first and second, and said fourth and fifth transistors, respectively, said third and sixth transistors are placed in a cut-off state.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-03-06 | 1987-09-05 | 1988-03-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-03-06 | 1991-09-05 | 1992-03-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-03-06 | 1995-09-05 | 1996-03-06 | $7700.00 | Window Closed / Lapsed |