Universal reset circuit for digital circuitry

Claim 2

A universal reset circuit for digital circuitry which monitors clock pulses and DC voltage and provides a reset command when detecting a low DC voltage or a missing clock pulse comprising: a constant voltage means for providing a stable reference voltage; a pulse timing means receiving said clock pulses for providing an output voltage level above said reference voltage when a regular clock pulse is received and allowing its output voltage to fall below said reference voltage when a clock pulse does not appear within a set time interval generating a low output pulse; a divider means connected across the DC voltage for producing a test voltage which is less than said reference voltage when a low DC voltage condition is experienced; a comparator which compares a combined input from said bridge means and said pulse timing means with said constant voltage means such that said comparator output will be high unless a missing clock pulse is detected which will produce a negative reset pulse or, unless a low DC voltage is detected which will produce a low output from said comparator.

Claim 3

The apparatus of claim 1, also comprising, a power reset delay means connected to the output of said comparator for holding the output of said comparator low for a set period of time after the DC voltage level has returned to normal.

Claim 4

The apparatus of claim 2, also comprising, a pulse shaping means connected between said pulse timing means and said comparator for setting the pulse width of the negative reset pulse produced at the output of said comparator.

Claim 6

The apparatus of claim 4 in which said resistor and capacitor in said timing circuit are of a value such that their product is greater than the clock pulse width.

Claim 7

The apparatus of claim 3 in which said pulse shaping means is a capacitor, the value of said capacitor determining the pulse width.

Claim 8

The apparatus of claim 3 in which said power reset delay means is an RC circuit containing a resistor and capacitor, the values of said resistors and capacitors can be varied to increase or decrease the time delay.

Claim 11

A universal reset circuit for digital circuitry which monitors clock pulses and DC voltage and produces a reset command when detecting a low DC voltage or a missing clock pulse, comprising: a 1% Zener diode, which produces a stable reference voltage; a first comparator which compares the clock pulses with said reference voltage producing a low voltage output with each clock pulse and a high output between clock pulses; a timing circuit containing a first capacitor and a first resistor is connected to the output of said first comparator to keep its output voltage below said reference voltage when a regular clock pulse train is inputed to said first comparator, but allows its output voltage to raise above said reference voltage when a clock pulse did not appear within a set time interval; a second comparator receives inputs from said timing circuit and said 1% Zener diode and produces a low voltage output pulse when the output voltage from said timer circuit raises above said reference voltage; a second capacitor connected to the output of said second comparator used to shape the low voltage output pulse produced by the second comparator; a divider connected across the DC voltage to provide a test voltage which is less than said reference voltage when a low DC voltage condition is experienced; a third comparator which compares a combined input from said divider and said second capacitor with said reference voltage, such that the output of said comparator will be high unless a missing clock pulse is detected, which will produce a negative reset pulse, or unless a low DC voltage is detected which will produce a low output from said comparator; and, an RC circuit connected to the output of said third comparator for holding the output of said comparator low for a set period of time after the DC voltage level has returned to normal.

Claim 12

A universal reset circuit for digital circuitry which monitors clock pulses and DC voltage and produces a reset command when detecting a low DC voltage or a missing clock pulse, comprising: a 1% Zener diode, which produces a stable reference voltage; a first comparator which compares the clock pulses with said reference voltage producing a low voltage output with each clock pulse and a high output between clock pulses; a timing circuit containing a first capacitor and a first resistor is connected to the output of said first comparator to keep its output voltage below said reference voltage when a regular clock pulse train is inputed to said first comparator, but allows its output voltage to raise above said reference voltage when a clock pulse did not appear within a set time interval; a second comparator receives inputs from said timing circuit and said 1% Zener diode and produces a low voltage output pulse when the output voltage from said timer circuit raises above said reference voltage; a second capacitor connected to the output of said second comparator used to shape the low voltage output pulse produced by the second comparator; a divider connected across the DC voltage to provide a test voltage which is less than said reference voltage when a low DC voltage condition is experienced; a third comparator which compares a combined input from said divider and said second capacitor with said reference voltage, such that the output of said comparator will be high unless a missing clock pulse is detected, which will produce a negative reset pulse, or unless a low DC voltage is detected which will produce a low output from said comparator; and, an RC circuit connected to the output of said third comparator for holding the output of said comparator low for a set period of time after the DC voltage level has returned to normal.