Modulator-demodulator for four level double amplitude modulation on quadrature carriers

Claim 2

A modulator operating with a double amplitude four-level modulation in phase quadrature on two carrier components, each of said two carrier components having a cyclic recurrence of bit time periods which define a basic time cycle, said two carrier components having a predetermined phase relationship with each other, said modulator comprising means for shifting the phases of two binary trains of digital input pulses in order to encode the two binary trains by one/half of a bit time period in the basic time cycle, means for modulating said respective carrier components responsive to said encoded trains of digital input pulses, and means for adding the two modulated carrier components in order to produce an output signal.

Claim 3

The modulator according to claim 1, further comprising means for differentially encoding one of the trains of digital pulses.

Claim 4

The modulator according to claim 2, further comprising first even-uneven separator means having an input terminal for receiving a first binary train of digital input pulses, encoding means having an input coupled to an output of said first even-uneven separator means for encoding said binary train of input pulses, second even-uneven separator means having an input coupled to an output of said encoding means, the second even-uneven separator means having two outputs for producing said two binary trains of digital input pulses, two sign control circuit means individually associated with the two outputs of said second even-uneven separator means, each of said two sign control circuit means changing the sign of every other signal which is applied to it, whereby said two sign control circuit means respectively cause a change of sign of every other signal appearing at said two outputs, two quaternary signal encoding means respectively coupled to outputs of said two circuit means, two multiplying means respectively coupled to the outputs of said two quaternary encoding means, means for applying said two carrier components to respective second inputs of each of said two multiplying means, the carrier component applied to each multiplying means having the same given frequency, said adding means being coupled to outputs of said two multiplying means.

Claim 5

A demodulator for a signal modulated by a double amplitude four-level modulation in phase quadrature on two carrier components, each of said two carrier components having a cyclic recurrence of bit time periods which define a basic time cycle, said two carrier components having a predetermined phase relationship with each other, said carrier components being modulated by two encoded binary trains of phase shifted digital input pulses, the phase shift being one/half of a bit time period; said demodulator comprising carrier recovery circuit means, clock recovery circuit means, multiplying means having two inputs; a signal input terminal coupled to an input of said carrier recovery circuit means, to an input of said clock recovery circuit means, and to an input of said multiplying means; the other input of said multiplying means being coupled to an output of said carrier recovery circuit; low-pass filter means coupled to an output of said multiplying means; sampler circuit means coupled to the output of said low-pass filter means, said sampler circuit means having a clock input which is coupled to the output of said clock recovery circuit means; a three threshold analog converter means coupled to the output of said sampler circuit means; decoder means coupled to one output of said analog converter means, said decoder means decoding the output of said sampler; and assembly means responsive to said decoder means for delivering an output corresponding to said modulation.

Claim 6

A demodulator for a signal modulated by a double amplitude four-level modulation in phase quadrature on two carrier components, each of said two carrier components having a cyclic recurrence of bit time periods which define a basic time cycle, said two carrier components having a predetermined phase relationship with each other, said carrier components being modulated by two encoded binary trains of phase shifted digital input pulses, the phase shift being one/half of a bit time period; said demodulator comprising carrier recovery circuit means, clock recovery circuit means, multiplying means having two inputs; a signal input terminal coupled to an input of said carrier recovery circuit means, to an input of said clock recovery circuit means, and to an input of said multiplying means; the other input of said multiplying means being coupled to an output of said carrier recovery circuit; low-pass filter means coupled to an output of said multiplying means; sampler circuit means coupled to the output of said low-pass filter means, said sampler circuit means having a clock input which is coupled to the output of said clock recovery circuit means; a three threshold analog converter means coupled to the output of said sampler circuit means; decoder means coupled to one output of said analog converter means, said decoder means decoding the output of said sampler; and assembly means responsive to said decoder means for delivering an output corresponding to said modulation.

Claim 7

A modulation/demodulation system for signals modulated by a double amplitude four-level modulation in phase quadrature on two carrier components, each of said two carrier components having a cyclic recurrence of bit time periods which define a basic time cycle, said two carrier components having a predetermined phase relationship with each other, said carrier components being modulated by two encoded binary trains of phase shifted digital input pulses; the modulator of said system comprising a first even-uneven separator means having an input terminal for receiving a first binary train of digital input pulses; encoding means having an input coupled to an output of said first even-uneven separator means for encoding said binary train of input pulses; second even-uneven separator means having an input coupled to an output of said encoding means, the second even-uneven separator means having two outputs for producing said two binary trains of digital input pulses; two sign control circuit means individually associated with the two outputs of said second even-uneven separator means, each of said two sign control circuit means changing the sign of every other signal which is applied to it, whereby said two sign control circuit means respectively cause a change of sign for every other signal appearing at said two outputs; two quaternary signal encoding means respectively coupled to outputs of said two circuit means; two multiplying means respectively coupled to the outputs of said two quaternary encoding means, means for applying said two carrier components to respective second inputs of each of said two multiplying means, the carrier component applied to each multiplying means having the same given frequency; and adding means coupled to outputs of said two mutiplying means, said adding means delivering the modulated signal at its output; said demodulator of said system comprising a carrier recovery circuit means, clock recovery circuit means, multiplying means having two inputs; a signal input terminal coupled to an input of said carrier recovery circuit means, to an input of said clock recovery circuit means, and to an input of said multiplying means; the other input of said multiplying means being coupled to an output of said carrier recovery circuit; low-pass filter means coupled to an output of said multiplying means; sampler circuit means coupled to the output of said low-pass filter means, said sampler circuit means having a clock input which is coupled to the output of said clock recovery circuit means; a three threshold analog converter means coupled to the output of said sampler circuit means; decoder means coupled to one output of said analog converter means, said decoder means decoding the output of said sampler; and assembly means responsive to said decoder means for delivering an output corresponding to said modulation.

Claim 8

A modulation/demodulation system for signals modulated by a double amplitude four-level modulation in phase quadrature on two carrier components, each of said two carrier components having a cyclic recurrence of bit time periods which define a basic time cycle, said two carrier components having a predetermined phase relationship with each other, said carrier components being modulated by two encoded binary trains of phase shifted digital input pulses; the modulator of said system comprising a first even-uneven separator means having an input terminal for receiving a first binary train of digital input pulses; encoding means having an input coupled to an output of said first even-uneven separator means for encoding said binary train of input pulses; second even-uneven separator means having an input coupled to an output of said encoding means, the second even-uneven separator means having two outputs for producing said two binary trains of digital input pulses; two sign control circuit means individually associated with the two outputs of said second even-uneven separator means, each of said two sign control circuit means changing the sign of every other signal which is applied to it, whereby said two sign control circuit means respectively cause a change of sign for every other signal appearing at said two outputs; two quaternary signal encoding means respectively coupled to outputs of said two circuit means; two multiplying means respectively coupled to the outputs of said two quaternary encoding means, means for applying said two carrier components to respective second inputs of each of said two multiplying means, the carrier component applied to each multiplying means having the same given frequency; and adding means coupled to outputs of said two mutiplying means, said adding means delivering the modulated signal at its output; said demodulator of said system comprising a carrier recovery circuit means, clock recovery circuit means, multiplying means having two inputs; a signal input terminal coupled to an input of said carrier recovery circuit means, to an input of said clock recovery circuit means, and to an input of said multiplying means; the other input of said multiplying means being coupled to an output of said carrier recovery circuit; low-pass filter means coupled to an output of said multiplying means; sampler circuit means coupled to the output of said low-pass filter means, said sampler circuit means having a clock input which is coupled to the output of said clock recovery circuit means; a three threshold analog converter means coupled to the output of said sampler circuit means; decoder means coupled to one output of said analog converter means, said decoder means decoding the output of said sampler; and assembly means responsive to said decoder means for delivering an output corresponding to said modulation.