Bipolar static semiconductor memory device with a high cell holding margin

Claim 2

A bipolar static type semiconductor memory device having a read mode, select mode, and a non-select mode, comprising: word lines; bit lines respectively intersecting corresponding ones of said word lines; flip-flop circuit memory cells respectively, operatively connected to corresponding ones of the word lines and corresponding ones of the bit lines; clamp means for clamping, in response to the non-select mode, the voltage of the respective bit lines to a voltage higher than the voltage of the respective bit lines during the read operation while said bipolar static type semiconductor memory device is selected.

Claim 3

A semiconductor memory device as claimed in claim 1, further comprising read transistors, respectively, operatively connected to corresponding ones of said bit lines and to said clamp means, wherein said clamp means comprises first means for clamping the base voltages of said read transistors connected to said corresponding one of the bit lines.

Claim 4

A semiconductor memory device according to claim 2, wherein said device is operatively connected to receive a chip select signal, a write enable signal and a data input signal, and further comprises: of sense amplifiers, respectively, operatively connected to corresponding ones of said bit lines, and wherein said respective or said read transistors are operatively connected between said corresponding ones of said bit lines and said respective sense amplifiers, and wherein said clamp means further comprises second means, operatively connected to said first means, for receiving said chip select signal and for placing said device in said select mode in accordance with said chip select signal; third means operatively connected to said first means, for receiving said write enable signal and said data input signal, and for placing said device in said read mode in accordance with said write enable signal, said first means including means for clamping the base voltages of said read transistors in response to said device being in said non-select mode, and said first means being responsive to said write enable signal and to said data signal in response to said device being in said select mode.

Claim 5

A semiconductor memory device as claimed in claim 1, wherein said device is operatively connected to receive a power supply voltage, and further comprises bit line selection control transistors, respectively, operatively connected between said power supply voltage and a corresponding one of said bit lines and to said clamp means, wherein said clamp means comprises first means for clamping the base voltages of said selection control transistors connected to said corresponding one the bit lines.

Claim 6

The semiconductor memory device as claimed in claim 4, wherein said device is operatively connected to receive a chip select signal, a write enable signal and a data signal, and further comprises: second means, operatively connected to said clamp means, for receiving said chip select signal and for placing said semiconductor memory device in said select mode in accordance with said chip select signal; third means, operatively connected to said clamp means, for receiving said write enable signal, and for placing said semiconductor memory device in said read mode in accordance with said write enable signal, wherein said first means comprises at least one current switch operatively connected to receive said data signal and operatively connected between a corresponding one of said selection control transistors and said second and third means, said current switch clamping the base voltages of said selection control transistors in response to said semiconductor memory device being in said non-select mode and said current switch responsive to said data signal and to said write enable signal in response to said semiconductor memory device in said select mode.