Abstract When frequency division is used as part of the clock signal regeneration process from a received data signal, a phase ambiguity may occur. A data signal receiver for a bi-phase modulated signal comprises a filter 1 feeding a sampling switch 2 which feeds a polarity detector 3 from which the decoded data is reproduced. The phase of the sampling switch 2 is controlled by the output 6-Q of a ÷2 frequency divider 6 which is driven by a phase-locked loop 5 which in turn is driven by a zero-crossing detector 4 at twice the bit frequency. A monitoring arrangement 8 has sampling switches 10 and 11 driven by outputs 6Q and 6-Q of the frequency divider 6. The data signal applied through a full-wave rectifier 9, is sampled at instants t o and t 1 , at twice the bit frequency. The outputs of the sample switches 10 and 11 are fed to minimum voltage detectors 12 and 13, respectively, which detect the minimum value of the samples over a number of cycles of the respective input and apply this value to the inputs of a comparator 14. If the output of detector 12 is more positive than that of detector 13, the receiver is correctly synchronized but if the output of detector 13 becomes more positive than that of the detector 12, the output of the comparator changes state and causes a pulse to be applied to input 6-1 of the divider to change the phase of the divider output 6-Q.
Inventors
👤 John M. Hale
Bibliographic Details
Application Number—
JurisdictionUS
Data Sourcegoogle_patents
Last Synchronized2026-11-02 16:22
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/027
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
116 words
An arrangement for checking the synchronization of a receiver for data signals having a power-versus-frequency spectrum comprising two sidebands located one on each side of a symbol frequency, the received data signal being synchronously sampled in each symbol interval at first and second instants which are half-a-symbol interval apart characterised in that the arrangement comprises means for detecting the minimum value of the sampled signal at each of the two instants and means for generating a check signal whose value is dependent on whether the minimum levels over a number of cycles of the input data of the signal sampled at the first instant, is greater than that of the signal sampled at the second instant.
Claim 2
Dependent Claim
116 words
An arrangement for checking the synchronization of a receiver for data signals having a power-versus-frequency spectrum comprising two sidebands located one on each side of a symbol frequency, the received data signal being synchronously sampled in each symbol interval at first and second instants which are half-a-symbol interval apart characterised in that the arrangement comprises means for detecting the minimum value of the sampled signal at each of the two instants and means for generating a check signal whose value is dependent on whether the minimum levels over a number of cycles of the input data of the signal sampled at the first instant, is greater than that of the signal sampled at the second instant.
Claim 3
Dependent Claim
93 words
An arrangement as claimed in claim 1, wherein the means for detecting the minimum value of the sampled signal at the first and second instants comprises a first and a second detector, each of said detectors comprising an input and an output, a first capacitor coupling said input to a negative supply line, a diode also connected to said input, and a parallel combination of a second capacitor and a resistor coupling said diode to a positive supply line, said output being connected to the junction of said diode and said parallel combination.
Claim 4
Dependent Claim
40 words
An arrangement as claimed in claim 2 further comprising a comparator having first and second inputs to which the outputs of the first and second detectors are respectively connected, a check signal being derived from the output of the comparator.