Digital capacitance measuring test set and test circuit incorporated therein

Claim 2

A capacitance measuring test set comprising: first means responsive to a first train of pulses when applied thereto for generating a second train of narrow width output trigger pulses; second means responsive to each of said trigger pulses, and to the capacitance of a capacitor when coupled thereto and charged relative to ground, for generating a third train of output pulses, the width of each of which pulses is directly proportional to the value of capacitance of a capacitor being measured at that instant in time; third means, responsive to each successive pulse of said third train, and to a coincident number of pulses of a fourth train of constant frequency pulses when applied thereto, for producing a fifth, time-dependent train of constant frequency pulses, the number of pulses in each of said fifth trains being dependent on the duration of the associated variable width pulse in said third train of pulses and, hence, also being proportional to the capacitance at that instant in time of a given capacitor when under measurement while coupled to said second means; fourth means for counting the number of pulses appearing in each fifth train of pulses, and for transforming that number into a digitized readout correlated with a time-coincident value of capacitance then exhibited by a capacitor while under measurement; fifth high speed switch means adapted to shunt a capacitor when connected to said second means, and being responsive to a given RESTORE pulse whenever applied thereto for effecting the shorting of each capacitor to ground, after having been previously charged to a predetermined voltage, at the completion of an associated capacitance measuring period; sixth means for sensing for the completion of each capacitance measurement period, and for controlling the start of the next measurement period, and multi-pulse train generating means for supplying said first and fourth pulse trains and said RESTORE pulses.

Claim 3

A capacitance measuring test set in accordance with claim 1 further including means for biasing said first, second, fourth and fifth means, and for charging a capacitor when under measurement.

Claim 4

A capacitance measuring test set in accordance with claim 2 wherein said multi-pulse train generating means includes a separate pulse generator for each of said first and fourth pulse trains.

Claim 5

A capacitance measuring test set in accordance with claim 2 wherein said multi-pulse train generating means comprises a programmed microcomputer, with each of said first and fourth pulse trains and said RESTORE pulses being supplied from different outputs thereof.

Claim 6

A capacitance measuring test circuit comprising: first means responsive to a first train of pulses when applied thereto for generating a second train of narrow width output trigger pulses; second means responsive to each of said trigger pulses, and to the capacitance of a capacitor when coupled thereto and charged relative to ground, for generating a third train of output pulses, the width of each of which pulses is directly proportional to the value of capacitance of a capacitor being measured at that instant in time; third means, responsive to each successive pulse of said third train, and to a coincident number of pulses of a fourth train of constant frequency pulses when applied thereto, for producing a fifth time-dependent train of constant frequency pulses, the number of pulses in each of said fifth trains being dependent on the duration of the associated variable width pulse in said train of pulses and, hence, also being proportional to the capacitance at that instant in time of a given capacitor when under measurement while coupled to said second means; fourth means for counting the number of pulses appearing in each fifth train of pulses, and for transforming that number into a digitized readout correlated with a time-coincident value of capacitance then exhibited by a capacitor while under measurement; fifth means for sensing for the completion of each capacitance measurement period, and for controlling the start of the next measurement period, and sixth means for sensing for a predetermined overflow count of pulses from said fourth means, with said sensed condition being chosen to be at least representative of a capacitor short in a capacitor initially expected to exhibit a predetermined nominal value of capacitance, and for providing a control signal to selectively indicate the existence of each such representative short, and to at least delay the start of the next measurement period until a new capacitor is coupled to said second means for testing.

Claim 7

A capacitance measuring test circuit comprising: first means responsive to a first train of pulses when applied thereto for generating a second train of narrow width output trigger pulses; second means responsive to each of said trigger pulses, and to the capacitance of a capacitor when coupled thereto and charged relative to ground, for generating a third train of output pulses, the width of each of which pulses is directly proportional to the value of capacitance of a capacitor being measured at that instant in time; third means, responsive to each successive pulse of said third train, and to a coincident number of pulses of a fourth train of constant frequency pulses when applied thereto, for producing a fifth time-dependent train of constant frequency pulses, the number of pulses in each of said fifth trains being dependent on the duration of the associated variable width pulse in said train of pulses and, hence, also being proportional to the capacitance at that instant in time of a given capacitor when under measurement while coupled to said second means; fourth means for counting the number of pulses appearing in each fifth train of pulses, and for transforming that number into a digitized readout correlated with a time-coincident value of capacitance then exhibited by a capacitor while under measurement; fifth means for sensing for the completion of each capacitance measurement period, and for controlling the start of the next measurement period, and sixth means for sensing for a predetermined overflow count of pulses from said fourth means, with said sensed condition being chosen to be at least representative of a capacitor short in a capacitor initially expected to exhibit a predetermined nominal value of capacitance, and for providing a control signal to selectively indicate the existence of each such representative short, and to at least delay the start of the next measurement period until a new capacitor is coupled to said second means for testing.

Claim 8

A capacitance measuring test circuit comprising: first means responsive to a first train of pulses when applied thereto for generating a second train of narrow width output trigger pulses; second means responsive to each of said trigger pulses, and to the capacitance of a capacitor when coupled thereto and charged relative to ground, for generating a third train of output pulses, the width of each of which pulses is directly proportional to the value of capacitance of a capacitor being measured at that instant in time; third means, responsive to each successive pulse of said third train, and to a coincident number of pulses of a fourth train of constant frequency pulses when applied thereto, for producing a fifth time-dependent train of constant frequency pulses, the number of pulses in each of said fifth trains being dependent on the duration of the associated variable width pulse in said third train of pulses and, hence, also being proportional to the capacitance at that instant in time of a given capacitor, when under measurement while coupled to said second means; fourth means for counting the number of pulses appearing in each fifth train of pulses and transforming that number into a digitized readout correlated with a time-coincident value of capacitance then exhibited by a capacitor while under measurement; fifth high speed switch means adapted to shunt a capacitor when connected to said second means-timer, and being responsive to a given RESTORE pulse whenever applied thereto for effecting the shorting of each such capacitor to ground, after having been previously charged to a predetermined voltage, at the completion of an associated capacitance measuring period, and sixth means for sensing that a capacitor condition that is chosen to be at least representative of a capacitor short in a capacitor initially expected to exhibit a predetermined nominal value of capacitance, and for providing a control signal to selectively indicate the existence of each such representative short, and to at least effect the delay of the start of the next measurement period until a new capacitor is coupled to said second means for testing.

Claim 9

A capacitance measuring test circuit comprising: first means responsive to a first train of pulses when applied thereto for generating a second train of narrow width output trigger pulses; second means responsive to each of said trigger pulses, and to the capacitance of a capacitor when coupled thereto and charged relative to ground, for generating a third train of output pulses, the width of each of which pulses is directly proportional to the value of capacitance of a capacitor being measured at that instant in time; third means, responsive to each successive pulse of said third train, and to a coincident number of pulses of a fourth train of constant frequency pulses when applied thereto, for producing a fifth time-dependent train of constant frequency pulses, the number of pulses in each of said fifth trains being dependent on the duration of the associated variable width pulse in said third train of pulses and, hence, also being proportional to the capacitance at that instant in time of a given capacitor, when under measurement while coupled to said second means; fourth means for counting the number of pulses appearing in each fifth train of pulses and transforming that number into a digitized readout correlated with a time-coincident value of capacitance then exhibited by a capacitor while under measurement; fifth high speed switch means adapted to shunt a capacitor when connected to said second means-timer, and being responsive to a given RESTORE pulse whenever applied thereto for effecting the shorting of each such capacitor to ground, after having been previously charged to a predetermined voltage, at the completion of an associated capacitance measuring period, and sixth means for sensing that a capacitor condition that is chosen to be at least representative of a capacitor short in a capacitor initially expected to exhibit a predetermined nominal value of capacitance, and for providing a control signal to selectively indicate the existence of each such representative short, and to at least effect the delay of the start of the next measurement period until a new capacitor is coupled to said second means for testing.

Claim 10

A capacitance measuring test circuit in accordance with claim 6 wherein said first means includes a monostable flip-flop, wherein said second means comprises a timer operated in a monostable mode, and wherein said fourth means includes digital counter means.

Claim 11

A capacitance measuring test circuit in accordance with claim 7 wherein said fourth means includes resettable digital counter means, and digital display means responsive to the output of said counter means for providing a direct visual numerical readout of the value of capacitance exhibited by a given capacitor when under measurement.

Claim 12

A capacitance measuring test circuit in accordance with claim 7 wherein said first means further includes a pulse generator for producing the first train of pulses applied to said associated monostable flip-flop.

Claim 13

A capacitance measuring test circuit in accordance with claim 6 further including means for applying timed RESTORE pulses to said switch means.

Claim 14

A capacitance measuring test circuit in accordance with claim 7 wherein the first train of pulses to be applied to said first-means monostable flip-flop, wherein the fourth train of constant frequency pulses to be applied to said third means and, wherein said RESTORE pulses to be applied to said switch means, are all respectively generated by separate, but sychronized, pulse generators.

Claim 15

A capacitance measuring test circuit in accordance with claim 11 wherein said fourth means further includes digital display means for providing a direct visual numerical readout of the value of capacitance exhibited by a given capacitor when under measurement.

Claim 16

A capacitance measuring test circuit in accordance with claim 7 wherein said first train of pulses to be applied to said first-means monostable flip-flop are generated by, and supplied from an output of, a programmed microcomputer.

Claim 17

A capacitance measuring test circuit in accordance with claim 13 wherein said RESTORE pulses are generated by, and supplied to said switch means from an output of, said programmed microcomputer.

Claim 18

A capacitance measuring test circuit in accordance with claim 7 wherein the first train of pulses to be applied to said first-means monostable flip-flop, wherein the fourth train of constant frequency pulses to be applied to said third means and, wherein said RESTORE pulses to be applied to said switch means, are all respectively generated by, and supplied from different outputs of, a programmed microcomputer.

Claim 19

A capacitance measuring test circuit in accordance with claim 14 wherein the fourth train of constant frequency pulses to be applied to said third means are supplied from an output of said programmed microcomputer, and wherein said test circuit further comprises pulse squaring means through which said fourth train of pulses are directed before being applied to said third means, the latter comprising a logic gate.

Claim 20

A capacitance test circuit in accordance with claim 16 wherein said fourth means includes resettable digital counter means, a digital decoder connected to said counter means and digital display means connected to said decoder for providing a direct visual numerical readout of the value of capacitance exhibited by a capacitor when under measurement, wherein said microcomputer generates resettable output pulses at a programmed output thereof for resetting said counter means, and wherein the digitized output of said counter means is applied as an input to said microcomputer selectively for storage, further processing and subsequent outputting under programmed control.

Claim 21

A capacitance measuring test set in accordance with claim 1 further including: means for sensing for a predetermined overflow count of pulses from said fourth means, with said sensed condition being chosen to be at least representative of a capacitor short in a capacitor initially expected to exhibit a predetermined nominal value of capacitance, and for providing a control signal to selectively indicate the existence of each such representative short, and to at least effect the delay of the start of the next measurement period until a new capacitor is coupled to said second means for testing.