US4428059A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Real time fill circuit
Assignee: BIOSOUND Inc 6405 CASTLEWAY COURT INDIANAPOLIS INDIANA 46250
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Filing: 1982-08-25
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Granted: 1984-01-24
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Expires: 2002-08-25
Abstract
Abstract There has been provided, a digital circuit for interpolating the intensity values between adjacent pulsed data signals. The interpolation includes, effectively, providing a plurality of shades of gray between adjacent received data. The interpolation data is applied to the display means to effectively fill the interstices between the adjacent image lines. When thus applied, the resultant image is one of a smooth transition between adjacent analog data thereby constituting a more readily readable and desirable display of the image.
Inventors
- 👤 James M. Gessert
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 18:28
CPC Classifications
G; G01; G01S; G01S7/00; G01S7/52; G01S7/523; G01S7/526; G01S7/53; G01S7/531; G06; G06F; G06F17/00; G06F17/10; G06F17/17; G06F17/175
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
184 words
Interpolating means for interpolating between successive units of significant digital data signals in a data stream separated by a number of data spaces, said interpolating means comprising: first means for determining the magnitude of the difference between successive units of significant digital data and for producing a corresponding digital difference signal; second means for determining the number of consecutive data spaces between successive units of significant digital data and for producing a corresponding digital space signal; third means connected to said first means and said second means to be responsive to said difference signal and said space signal to produce a digital fraction value signal representing a corresponding fractional portion of said difference signal; means for sequentially incrementing said successive significant digital data signals in said data stream with said digital fractional value signal in accordance with said digital data space signal whereby to provide incremented value signals corresponding in number to the respective digital data space signals; and means for introducing said incremented value signals seriatim between adjacent ones of said significant digital data signals to provide an interpolated digital data signal stream.
Claim 2
Dependent Claim
184 words
Interpolating means for interpolating between successive units of significant digital data signals in a data stream separated by a number of data spaces, said interpolating means comprising: first means for determining the magnitude of the difference between successive units of significant digital data and for producing a corresponding digital difference signal; second means for determining the number of consecutive data spaces between successive units of significant digital data and for producing a corresponding digital space signal; third means connected to said first means and said second means to be responsive to said difference signal and said space signal to produce a digital fraction value signal representing a corresponding fractional portion of said difference signal; means for sequentially incrementing said successive significant digital data signals in said data stream with said digital fractional value signal in accordance with said digital data space signal whereby to provide incremented value signals corresponding in number to the respective digital data space signals; and means for introducing said incremented value signals seriatim between adjacent ones of said significant digital data signals to provide an interpolated digital data signal stream.
Claim 3
Dependent Claim
24 words
Interpolating means as set forth in claim 1 wherein said first means comprises a digital summing circuit means for deriving said digital difference signal.
Claim 4
Dependent Claim
96 words
Interpolating means as set forth in claim 2 wherein said first means further includes circuit means for connecting a current significant digital data signals to a first input of said summing circuit means and an old value register means for temporary storage of an immediately previous significant digital data signal, said register means having an output connected to a second input of said summing circuit means whereby said summing circuit is operative to compare said current significant digital data signal with said signal stored in said old value register and to provide an output difference signal.
Claim 5
Dependent Claim
29 words
Interpolating means as set forth in claim 1 wherein said second means includes means for detecting said data spaces and counter means for determining said number of data spaces.
Claim 6
Dependent Claim
36 words
Interpolating means as set forth in claim 3 wherein said second means includes means for detecting said data spaces and counter means for counting the number of said data spaces between said successive significant digital signals.
Claim 7
Dependent Claim
57 words
Interpolating means as set forth in claim 5 wherein said third means comprises an addressable storage means having stored therein a table of digital fractional values, individual ones of said fractional values being addressable by said digital difference signal and said digital space signal to select from said table said corresponding fractional portion of said difference signal.
Claim 8
Dependent Claim
110 words
Interpolating means as set forth in claim 6 further including an output register means having an input and an output circuit means, and wherein said means for sequentially incrementing comprises an incrementing digital summing means having a first input connected to the output of said addressable storage means, an output connected to said input of said output register means, said output of said register means being connected to a second input of said incrementing digital summing means whereby to sequentially sum the output signal from said output register with said corresponding fractional portion of said difference signal between said successive units of significant digital data signals in said data stream.
Claim 9
Dependent Claim
174 words
Image data display apparatus comprising: means for transmitting and, after a time period, receiving reflected pulsed analog image data signal; means for converting said analog image data signals to significant digital image data signals; memory means for storing said significant digital image data signals in a predetermined array in said memory means in which successive units of said significant digital image data signals are separated by a number of data spaces such number varying with the time period; circuit means including digital interpolating means for providing a number of interpolative digital fractional value signals in said data spaces between said successive units of significant digital image data signals the number of said interpolative fractional value signals being a function of the number of said data spaces; said circuit means further including means for converting the significant digital image data signals and said interpolative digital fractional value signals from said interpolating means to output analog signals; and means for controlling the Z-axis modulation of an image display apparatus in accordance with said output analog signals.
Claim 10
Dependent Claim
174 words
Image data display apparatus comprising: means for transmitting and, after a time period, receiving reflected pulsed analog image data signal; means for converting said analog image data signals to significant digital image data signals; memory means for storing said significant digital image data signals in a predetermined array in said memory means in which successive units of said significant digital image data signals are separated by a number of data spaces such number varying with the time period; circuit means including digital interpolating means for providing a number of interpolative digital fractional value signals in said data spaces between said successive units of significant digital image data signals the number of said interpolative fractional value signals being a function of the number of said data spaces; said circuit means further including means for converting the significant digital image data signals and said interpolative digital fractional value signals from said interpolating means to output analog signals; and means for controlling the Z-axis modulation of an image display apparatus in accordance with said output analog signals.
Claim 11
Dependent Claim
164 words
Image data display apparatus as set forth in claim 8 wherein said interpolating means comprises: first means for determining the magnitude of the difference between successive units of significant digital image data and for producing a corresponding digital difference signal; second means for determining the number of consecutive data spaces between successive units of significant digital image data and means for producing a corresponding digital space signal; third means connected to said first means and said second means to be responsive to said difference signal and said space signal to produce a digital fractional value signal representing a corresponding fractional portion of said difference signal; means for sequentially incrementing said successive significant digital image data signals with said digital fractional value signals in accordance with said digital data space signal whereby to provide incremented value signals corresponding in number to said digital data space signals; and means for introducing said incremented value signals seriatim between adjacent ones of said significant digital image data signals.
Claim 12
Dependent Claim
59 words
Image data display means as set forth in claim 9 wherein said third means comprises an addressable storage means having stored therein a table of digital fractional values, individual ones of said fractional values being addressable by said digital difference signal and said digital space signal to select from said table said corresponding fractional portion of said difference signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-01-23 | 1987-07-25 | 1988-01-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-01-23 | 1991-07-25 | 1992-01-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-01-23 | 1995-07-25 | 1996-01-24 | $7700.00 | Window Closed / Lapsed |