US4428047A — Addressing a control ROM in a microcoded single-c…

Claim 1

Independent Claim 190 words

A microprocessor device comprising: a semiconductor integrated circuit having an arithmetic/logic unit, a plurality of registers for storing data and memory addresses, an instruction register, parallel bus means for interconnecting the arithmetic/logic unit and the registers, and control means having an input coupled to the instruction register and generating control signal outputs coupled to the arithmetic/logic unit, to the bus means and to the registers to control operation thereof in response to instruction words, all within the integrated circuit, wherein the control means includes a read-only-array having an address input coupled to said input of the control means and having outputs coupled to said control signal outputs, said control means having addressing means for applying sequences of addresses to said address input to define an operation selected by an instruction word in the instruction register, each sequence including a group dispatch to select an addressing mode using one or more of said addresses and subsequently including a function dispatch to select an arithmetic/logic function using one or more of said addresses, the group and function dispatches being controlled by fields of bits of said instruction word in said instruction register.

Claim 2

Dependent Claim 190 words

A microprocessor device comprising: a semiconductor integrated circuit having an arithmetic/logic unit, a plurality of registers for storing data and memory addresses, an instruction register, parallel bus means for interconnecting the arithmetic/logic unit and the registers, and control means having an input coupled to the instruction register and generating control signal outputs coupled to the arithmetic/logic unit, to the bus means and to the registers to control operation thereof in response to instruction words, all within the integrated circuit, wherein the control means includes a read-only-array having an address input coupled to said input of the control means and having outputs coupled to said control signal outputs, said control means having addressing means for applying sequences of addresses to said address input to define an operation selected by an instruction word in the instruction register, each sequence including a group dispatch to select an addressing mode using one or more of said addresses and subsequently including a function dispatch to select an arithmetic/logic function using one or more of said addresses, the group and function dispatches being controlled by fields of bits of said instruction word in said instruction register.

Claim 3

Dependent Claim 38 words

A microprocessor device according to claim 1 wherein the group dispatch selects one of a first set of said addresses each being defined by a base address and a plurality of bits from one of said instruction words.

Claim 4

Dependent Claim 35 words

A microprocessor device according to claim 1 wherein the function dispatch uses a second set of addresses each being defined by a base address and a plurality of bits from one of said instruction words.

Claim 5

Dependent Claim 44 words

A microprocessor device according to claim 2 wherein some of said addresses of the first set are the first ones of sequences of addresses to define different addressing modes and at least one address is used in a plurality of such sequences of addresses.

Claim 6

Dependent Claim 39 words

A microprocessor device according to claim 1 wherein a read-only-memory is included in said integrated circuit for storing said instruction words, the read-only-memory having an output to said instruction register for transferring instruction words one-at-a-time to the control means.

Claim 7

Dependent Claim 228 words

A microprocessor device comprising: a semiconductor integrated circuit having an arithmetic/logic unit, a plurality of registers for storing data and memory addresses, parallel bus means for interconnecting the arithmetic/logic unit and the registers, and control means connected to receive instruction words and having output control signals coupled to the arithmetic/logic unit and the bus means and registers for controlling operation thereof in response to said instruction words, all within the integrated circuit; and wherein the control means includes a read-only-array having an address input and a multi-bit command output, and the control means includes addressing means having an output coupled to the address input of the read-only array for applying sequences of addresses to said address inpurt, each said sequence defining an operation selected by one of said instruction words and including a plurality of microcode states, the array containing one microcode state for each address to said address input, the maximum number of microcode states being defined by the number of bits of the address input, and said addressing means includes dispatch means for applying a jump address of a plurality of bits from said command output to said address input of the read-only array to select a next microcode state, the maximum number of said plurality of bits of said jump address being equal to the number of bits of said address input of said read-only-array.

Claim 8

Dependent Claim 228 words

A microprocessor device comprising: a semiconductor integrated circuit having an arithmetic/logic unit, a plurality of registers for storing data and memory addresses, parallel bus means for interconnecting the arithmetic/logic unit and the registers, and control means connected to receive instruction words and having output control signals coupled to the arithmetic/logic unit and the bus means and registers for controlling operation thereof in response to said instruction words, all within the integrated circuit; and wherein the control means includes a read-only-array having an address input and a multi-bit command output, and the control means includes addressing means having an output coupled to the address input of the read-only array for applying sequences of addresses to said address inpurt, each said sequence defining an operation selected by one of said instruction words and including a plurality of microcode states, the array containing one microcode state for each address to said address input, the maximum number of microcode states being defined by the number of bits of the address input, and said addressing means includes dispatch means for applying a jump address of a plurality of bits from said command output to said address input of the read-only array to select a next microcode state, the maximum number of said plurality of bits of said jump address being equal to the number of bits of said address input of said read-only-array.

Claim 9

Dependent Claim 32 words

A microprocessor device according to claim 6 wherein said dispatch means selects at least one of said addresses defined by said jump address and a plurality of bits from an instruction word.

Claim 10

Dependent Claim 37 words

A microprocessor device according to claim 7 wherein the dispatch means selects one of a plurality of sequences of addresses, each sequence being defined by a jump address and a plurality of bits from an instruction word.

Claim 11

Dependent Claim 34 words

A microprocessor device according to claim 8 wherein the first addresses of sequences of addresses use bits from an instruction word and subsequent addresses of said sequences of addresses use only a jump address.

Claim 12

Dependent Claim 41 words

A microprocessor device according to claim 8 wherein the integrated circuit includes a read-only-memory for storing programs consisting of sequences of said instruction words, and the read-only-memory has an output coupled to said control means to transfer said instruction words one-at-a-time.

Claim 13

Independent Claim 162 words

A method of operating a microprocessor system of the type having an arithmetic/logic unit, a plurality of data/address registers, an instruction register, and a memory, with data/address bus means for accessing the arithmetic/logic unit, the data/address registers, the instruction register and the memory; the system having a microinstruction store with a given number of states and addressing means for the microinstruction store to select one state based on a multi-bit address input; comprising the steps of: generating a first multi-bit address for said addressing means based upon a given instruction in the instruction register, executing a sequence of microinstructions from said store beginning at said first address and continuing with subsequent multi-bit addresses generated directly from outputs of the microinstruction store, said outputs containing the same number of bits as said multi-bit address input whereby jumps to any of said states in the entire microinstruction store are possible, and thereafter fetching another instruction from said memory for loading in said instruction register.

Claim 14

Independent Claim 162 words

A method of operating a microprocessor system of the type having an arithmetic/logic unit, a plurality of data/address registers, an instruction register, and a memory, with data/address bus means for accessing the arithmetic/logic unit, the data/address registers, the instruction register and the memory; the system having a microinstruction store with a given number of states and addressing means for the microinstruction store to select one state based on a multi-bit address input; comprising the steps of: generating a first multi-bit address for said addressing means based upon a given instruction in the instruction register, executing a sequence of microinstructions from said store beginning at said first address and continuing with subsequent multi-bit addresses generated directly from outputs of the microinstruction store, said outputs containing the same number of bits as said multi-bit address input whereby jumps to any of said states in the entire microinstruction store are possible, and thereafter fetching another instruction from said memory for loading in said instruction register.

Claim 15

Dependent Claim 33 words

A method according to claim 11 including the step of generating a second address for said addressing means from said given instruction in the instruction register before said step of fetching another instruction.

Claim 16

Dependent Claim 19 words

A method according to claim 12 wherein a second sequence of microinstructions is executed beginning at said second address.

Claim 17

Dependent Claim 18 words

A method according to claim 11 wherein all said steps are exeucted within a single semiconductor integrated circuit.

Claim 18

Dependent Claim 30 words

A method according to claim 14 wherein said sequence of microinstructions include branches using address bits from the instruction register and other branches using address bits from a status register.

Claim 19

Dependent Claim 177 words

A microcomputer comprising: first memory means of the read-only type containing program and second memory means of the read/write type containing data, bus means and a CPU, all in a single semiconductor unit, the CPU including arithmetic/logic means, and including address registers for accessing the memory means via said bus means, and microprogramming control means included in the CPU for receiving program instructions from the first memory means via said bus means and generating a sequence of microinstruction states in response to each of said program instructions, said control means including an array of rows and columns of cells with selector means for actuating only one row for each microinstruction state, the columns providing output control signals for each microinstruction state and also providing a multi-bit address output and a dispatch control output, said multi-bit address output and said dispatch control output both being coupled to an input of said selector means whereby the selector means actuates a row dependent upon at least part of said multi-bit address output and also dependent upon said dispatch control output.

Claim 20

Dependent Claim 177 words

A microcomputer comprising: first memory means of the read-only type containing program and second memory means of the read/write type containing data, bus means and a CPU, all in a single semiconductor unit, the CPU including arithmetic/logic means, and including address registers for accessing the memory means via said bus means, and microprogramming control means included in the CPU for receiving program instructions from the first memory means via said bus means and generating a sequence of microinstruction states in response to each of said program instructions, said control means including an array of rows and columns of cells with selector means for actuating only one row for each microinstruction state, the columns providing output control signals for each microinstruction state and also providing a multi-bit address output and a dispatch control output, said multi-bit address output and said dispatch control output both being coupled to an input of said selector means whereby the selector means actuates a row dependent upon at least part of said multi-bit address output and also dependent upon said dispatch control output.

Claim 21

Dependent Claim 27 words

A microcomputer according to claim 16 wherein the dispatch control output defines a multi-bit address input to said selector means using specified bits of a program instruction.

Claim 22

Dependent Claim 30 words

A microcomputer according to claim 17 wherein the dispatch control output defines part of said multi-bit address input as one of a plurality of different fields of a program instruction.

Claim 23

Dependent Claim 26 words

A microcomputer according to claim 18 wherein the dispatch control output alternatively defines part of said multi-bit address input to include bits from a condition-responsive store.

Claim 24

Dependent Claim 34 words

A microcomputer according to claim 19 wherein the dispatch control output alternatively defines part of said multi-bit address input to include at least one bit from one of a plurality of different condition-responsive stores.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1987-01-23	1987-07-25	1988-01-24	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1991-01-23	1991-07-25	1992-01-24	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1995-01-23	1995-07-25	1996-01-24	$7700.00	Window Closed / Lapsed

Addressing a control ROM in a microcoded single-chip microcomputer using the output signals of the control ROM

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