Television digital data frame with error detection

Claim 3

The method of claim 1 that includes the additional method steps of; (a) recording transmitted said standard video signal format containing said digital information, and (b) reproducing the recorded information.

Claim 4

The method of claim 1 that includes the additional method steps for determining validity, of; (a) storing in order the digital information on each line for which a valid code check occurs in the first field of a frame, and (b) storing in order the digital information on each line for which a valid code check did not occur in the first field, but which does occur in the second field of a frame.

Claim 5

The method of claim 3, that includes the additional method steps for determining validity, of; (a) reordering the line number sequence in the second field by approximately half the number of lines in the field, to thereby avoid imperfections in a recording medium.

Claim 6

The method of claim 3, which additionally includes; (a) combining the stored valid information into a complete field sequence, (b) reading out said stored received field sequence, and (c) converting the read-out field sequence to alpha-numeric characters for display.

Claim 7

The method of claim 5, which includes the additional method steps of; (a) reading out the digital information of said received field sequence, and (b) converting the read-out digital information to microprocessor operating instructions.

Claim 8

Apparatus for communicating digital information, comprising; (a) a source of digital information (1), (b) a first microprocessor (2), having a memory (3), to control and also respond to said source of digital information, and to place the same, addressed, in said memory, (c) a source of standard video signal synchronizing waveform, (d) a video random access memory (20) to accept said digital information, (e) a direct memory access (5) connected to said video random access memory to accept said digital information from said video random access memory, at video speed, except at such times as pulses occur in said standard video signal synchronizing waveform, (f) a random access memory (21) to accept said digital information from said direct memory access at video speed and to output the same at video speed, synchronized with said standard video signal synchronizing waveform, (g) means (27) to insert check bits for verification, coding (26), and television synchronization (22), upon the lines in said frame, (h) means to transmit (7) said frame, (i) means to receive (7') said frame, (j) a vertical interval time code reader (9) for identifying the received frame of digital information, (k) a second microprocessor (11), having a memory, to accept the received frame of digital information, (l) means to form alpha-numeric characters (15) from said received frame of digital information, and (m) means (15) to display said received alpha-numeric characters.

Claim 9

Apparatus for communicating digital information, comprising; (a) a source of digital information (1), (b) a first microprocessor (2), having a memory (3), to control and also respond to said source of digital information, and to place the same, addressed, in said memory, (c) a source of standard video signal synchronizing waveform, (d) a video random access memory (20) to accept said digital information, (e) a direct memory access (5) connected to said video random access memory to accept said digital information from said video random access memory, at video speed, except at such times as pulses occur in said standard video signal synchronizing waveform, (f) a random access memory (21) to accept said digital information from said direct memory access at video speed and to output the same at video speed, synchronized with said standard video signal synchronizing waveform, (g) means (27) to insert check bits for verification, coding (26), and television synchronization (22), upon the lines in said frame, (h) means to transmit (7) said frame, (i) means to receive (7') said frame, (j) a vertical interval time code reader (9) for identifying the received frame of digital information, (k) a second microprocessor (11), having a memory, to accept the received frame of digital information, (l) means to form alpha-numeric characters (15) from said received frame of digital information, and (m) means (15) to display said received alpha-numeric characters.

Claim 10

The apparatus of claim 7, in which said digital information is synchronized with said standard video signal synchronizing waveform, for combination therewith by; (a) clock means (24) connected to said random access memory (21) and to said source of standard video signal synchronizing waveform for the alternate actuation thereof.