US4425552A
Expired / Lapsed
US
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Direct-type binary frequency synthesizer
Assignee: SP-MICROWAVE Inc
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Filing: 1981-08-17
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Granted: 1984-01-10
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Expires: 2001-08-17
Abstract
Abstract An apparatus including means for providing at least five fixed internal frequency signals having five different values of frequencies in which all of said frequencies are coupled into a first processor stage comprised of a single pole double throw switch controlled by a first input bit command signal for selecting either of two of said five frequencies for coupling into a first frequency mixer. A third frequency signal is also coupled into the first frequency mixer which provides a first difference frequency output signal that is coupled into a second frequency mixer. The second frequency mixer is coupled to a second single pole double throw switch controlled by a second input bit command signal for selecting either of the fourth or the fifth of said five frequencies. The difference output signal of the second frequency mixer is coupled to a frequency divider capable of division by four. The output signal produced by the frequency divider is a discrete synthesizer frequency output signal selected from a range of frequency output signals in accordance with the input bit command signal.Additional identical processor stages may be added to provide smaller increments between the selectable discrete synthesizer frequency output signals.
Inventors
- 👤 Ronald C. Stirling
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 18:29
CPC Classifications
H; H03; H03B; H03B21/00; H03B21/01; H03B21/04
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
587 words
A direct-type binary frequency synthesizer, providing an output signal, comprising: frequency generator means for providing at least five output signals having, respectively, predetermined frequencies F 1 , F 2 , F 3 , F 4 , and F 5 such that F 1 -F 3 =F 4 -4F 3 , and F 5 -F 4 =2F 1 -2F 2 ; binary bit command signal means for providing binary bit command signals; at least one processor stage, a processor stage providing an output signal, and having: first switch means, coupled to said frequency generator means and said binary bit command signal means, for receiving said binary bit command signals and said signals having frequencies F 1 and F 2 , and for selectively providing, in response to said binary bit command signals, an output signal of either said signal having frequency F 1 or said signal having frequency F 2 ; first mixer means, responsive to said output signal of said first switch means, and a second input signal, for providing an output signal having a frequency which is the frequency difference between said output signal of said first switch means and said second input signal; second switch means, coupled to said frequency generator means and said binary bit command signal means, for receiving said binary bit command signals and said signals having frequencies F 4 and F 5 , and for selectively providing, in response to said binary bit command signals, an output signal of either said signal having frequency F 4 or said signal having frequency F 5 ; second mixer means, responsive to said output signal of said second switch means and said output signal of said first mixer means, for providing an output signal having a frequency which is the frequency difference between said output signal of said first mixer means and said output signal of said second switch means; and divider means, responsive to said output signal of said second mixer means, for providing an output signal having a frequency which is one-quarter of the frequency of said output signal of said second mixer means, said output signal of said divider means being said output signal of said processor stage, a first processor stage of said at least one processor stage having said signal with frequency F 3 provided by said frequency generator means as said second input signal to which said first mixer means is responsive, each additional processor stage of said at least one processor stage being consecutively numbered, and having the output signal of the preceding processor stage as said second input signal to which said first mixer means is responsive, the output of the highest numbered processor stage being said output of said frequency synthesizer, whereby the frequency of said output signal of said frequency synthesizer is F 3 +(D/4 N ) F S , where F S is (F 5 -F 4 )/2, N is the number of processor stages, and D is the base 10 number which is equivalent to the base 2 number which results from forming, for each processor stage, an ordered pair whose right entry is the frequency of the output signal of said first switch means, and whose left entry is the frequency of the output signal of said second switch means; and, from concatenating from right to left the ordered pairs of consecutively, increasingly numbered processor stages; and, from replacing, within the sequence so formed, F 1 by 0, F 2 by 1, F 4 by 0, and F 5 by 1.
Claim 2
Dependent Claim
587 words
A direct-type binary frequency synthesizer, providing an output signal, comprising: frequency generator means for providing at least five output signals having, respectively, predetermined frequencies F 1 , F 2 , F 3 , F 4 , and F 5 such that F 1 -F 3 =F 4 -4F 3 , and F 5 -F 4 =2F 1 -2F 2 ; binary bit command signal means for providing binary bit command signals; at least one processor stage, a processor stage providing an output signal, and having: first switch means, coupled to said frequency generator means and said binary bit command signal means, for receiving said binary bit command signals and said signals having frequencies F 1 and F 2 , and for selectively providing, in response to said binary bit command signals, an output signal of either said signal having frequency F 1 or said signal having frequency F 2 ; first mixer means, responsive to said output signal of said first switch means, and a second input signal, for providing an output signal having a frequency which is the frequency difference between said output signal of said first switch means and said second input signal; second switch means, coupled to said frequency generator means and said binary bit command signal means, for receiving said binary bit command signals and said signals having frequencies F 4 and F 5 , and for selectively providing, in response to said binary bit command signals, an output signal of either said signal having frequency F 4 or said signal having frequency F 5 ; second mixer means, responsive to said output signal of said second switch means and said output signal of said first mixer means, for providing an output signal having a frequency which is the frequency difference between said output signal of said first mixer means and said output signal of said second switch means; and divider means, responsive to said output signal of said second mixer means, for providing an output signal having a frequency which is one-quarter of the frequency of said output signal of said second mixer means, said output signal of said divider means being said output signal of said processor stage, a first processor stage of said at least one processor stage having said signal with frequency F 3 provided by said frequency generator means as said second input signal to which said first mixer means is responsive, each additional processor stage of said at least one processor stage being consecutively numbered, and having the output signal of the preceding processor stage as said second input signal to which said first mixer means is responsive, the output of the highest numbered processor stage being said output of said frequency synthesizer, whereby the frequency of said output signal of said frequency synthesizer is F 3 +(D/4 N ) F S , where F S is (F 5 -F 4 )/2, N is the number of processor stages, and D is the base 10 number which is equivalent to the base 2 number which results from forming, for each processor stage, an ordered pair whose right entry is the frequency of the output signal of said first switch means, and whose left entry is the frequency of the output signal of said second switch means; and, from concatenating from right to left the ordered pairs of consecutively, increasingly numbered processor stages; and, from replacing, within the sequence so formed, F 1 by 0, F 2 by 1, F 4 by 0, and F 5 by 1.
Claim 3
Dependent Claim
167 words
An apparatus as in claim 1 wherein: said frequency generator means comprises a crystal controlled oscillator, and a synchronized signal generator coupled to said oscillator, said first switch means comprises a first single pole double throw switch, said first mixer means comprises: a first mixer, coupled to said first switch; and a first band pass filter, coupled to said first mixer, tuned to the pass band of the frequency difference between an output signal of said first switch and said second input signal, said second switch means comprises a second single pole double throw switch, said second mixer means comprises: a second mixer, coupled between said second switch and said first filter; a second band pass filter, coupled to said second mixer, tuned to the pass band of the frequency difference between an output signal of said second switch and an output signal of said first filter; and an amplifier, coupled to said second filter, and said divider means comprises a digital divider, coupled to said amplifier.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-01-09 | 1987-07-11 | 1988-01-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-01-09 | 1991-07-11 | 1992-01-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-01-09 | 1995-07-11 | 1996-01-10 | $7700.00 | Window Closed / Lapsed |