US4421995A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Timing discriminator using leading-edge extrapolation
Assignee: United States Department of Energy
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Filing: 1981-07-30
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Granted: 1983-12-20
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Expires: 2001-07-30
Abstract
Abstract A discriminator circuit to recover timing information from slow-rising pulses by means of an output trailing edge, a fixed time after the starting corner of the input pulse, which is nearly independent of risetime and threshold setting. This apparatus comprises means for comparing pulses with a threshold voltage; a capacitor to be charged at a certain rate when the input signal is one-third threshold voltage, and at a lower rate when the input signal is two-thirds threshold voltage; current-generating means for charging the capacitor; means for comparing voltage capacitor with a bias voltage; a flip-flop to be set when the input pulse reaches threshold voltage and reset when capacitor voltage reaches the bias voltage; and a clamping means for discharging the capacitor when the input signal returns below one-third threshold voltage.
Inventors
- 👤 Bernard Gottschalk
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 14:52
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/08; H03K5/082; H03K5/153
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
249 words
A timing discriminator for recovering timing information from slow-rising input pulses, which comprises: a voltage divider for setting a threshold voltage at a predetermined voltage; a first means for comparing said input pulses with said threshold voltage; a flip-flop circuit means connected to said first comparing means and set by said first comparing means when said input pulses reach said threshold voltage; a second means for comparing said input pulses with two-thirds said threshold voltage; a third means for comparing said input pulses with one-third said threshold voltage; a first means for generating current connected to said third comparing means and switched on by said third comparing means when said input pulses reach one-third of said threshold voltage; a second means for generating current connected to said second comparing means switched on by said third comparing means when said input pulses reach one-third of said threshold voltage and switched off by said second comparing means when said input pulses reach two-thirds of said threshold voltage; a capacitor connected to said first and second generating means and charged by said first and second generating means; a bias divider for setting a bias voltage at a predetermined level; a fourth means for comparing said capacitor voltage with said bias voltage and for resetting said flip-flop circuit means when said capacitor voltage reach said bias voltage; and a clamping circuit means connected to said fourth comparing means and said capacitor for discharging said capacitor when said capacitor voltage reaches said bias voltage.
Claim 2
Dependent Claim
249 words
A timing discriminator for recovering timing information from slow-rising input pulses, which comprises: a voltage divider for setting a threshold voltage at a predetermined voltage; a first means for comparing said input pulses with said threshold voltage; a flip-flop circuit means connected to said first comparing means and set by said first comparing means when said input pulses reach said threshold voltage; a second means for comparing said input pulses with two-thirds said threshold voltage; a third means for comparing said input pulses with one-third said threshold voltage; a first means for generating current connected to said third comparing means and switched on by said third comparing means when said input pulses reach one-third of said threshold voltage; a second means for generating current connected to said second comparing means switched on by said third comparing means when said input pulses reach one-third of said threshold voltage and switched off by said second comparing means when said input pulses reach two-thirds of said threshold voltage; a capacitor connected to said first and second generating means and charged by said first and second generating means; a bias divider for setting a bias voltage at a predetermined level; a fourth means for comparing said capacitor voltage with said bias voltage and for resetting said flip-flop circuit means when said capacitor voltage reach said bias voltage; and a clamping circuit means connected to said fourth comparing means and said capacitor for discharging said capacitor when said capacitor voltage reaches said bias voltage.
Claim 3
Dependent Claim
44 words
The timing discriminator of claim 1, further including a leakage resistor connected across said capacitor for discharging said capacitor when said input pulses switching on said first and second generating means are not long enough to raise said capacitor voltage to said bias voltage.
Claim 4
Dependent Claim
39 words
The timing discriminator of claim 2, further including a nonlinear correction circuit means connected to said first and second generating means for maintaining the linearity deviation of said timing information at a minimum, when said input pulses are nonlinear.
Claim 5
Dependent Claim
22 words
The timing discriminator of claim 3, wherein said first and second generating means are transistors switched on by said third comparing means.
Claim 6
Dependent Claim
29 words
The timing discriminator of claim 4, wherein a voltage inverter means for changing voltage polarity is connected between said third comparing means and said first and second generating means.
Claim 7
Dependent Claim
57 words
The timing discriminator of claim 1, wherein said clamping circuit means consist of two identical inverters controlled by said fourth comparing means and connected to said capacitor and said bias divider, to provide clamping for said capacitor until said input pulses are below one-third said threshold voltage and until said first and second generating means are off.
Claim 8
Dependent Claim
111 words
A timing device for recovering timing information from input pulses which comprises: means to start a square wave when said input pulses reach a predetermined threshold voltage; current-generating means responsive to said input pulses to be activated to supply a high charging current when said input pulses reach one-third threshold voltage and to supply charging current that is lower than said high current when said input pulses reach two-third threshold voltage; a capacitor connected to said current-generating means for receiving charging current from said current-generating means; and means for comparing said capacitor voltage with a predetermined bias voltage to end said square wave when said capacitor and bias voltages are equal.
Claim 9
Dependent Claim
111 words
A timing device for recovering timing information from input pulses which comprises: means to start a square wave when said input pulses reach a predetermined threshold voltage; current-generating means responsive to said input pulses to be activated to supply a high charging current when said input pulses reach one-third threshold voltage and to supply charging current that is lower than said high current when said input pulses reach two-third threshold voltage; a capacitor connected to said current-generating means for receiving charging current from said current-generating means; and means for comparing said capacitor voltage with a predetermined bias voltage to end said square wave when said capacitor and bias voltages are equal.
Claim 10
Dependent Claim
17 words
The timing device of claim 7, further comprising means connected across said capacitor for discharging said capacitor.
Claim 11
Dependent Claim
22 words
The timing device of claim 7, further comprising means connected to said current-generating means for correction of nonlinearity of said input pulses.
Claim 12
Dependent Claim
35 words
The timing device of claim 8, wherein said discharging means includes a resistor for alternatively discharging said capacitor when said capacitor voltage is unable to reach said predetermined bias voltage for ending said square wave.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-12-19 | 1987-06-20 | 1987-12-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-12-19 | 1991-06-20 | 1991-12-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-12-19 | 1995-06-20 | 1995-12-20 | $7700.00 | Window Closed / Lapsed |