US4421952A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multi-frequency busy signal synthesizing circuitry
Assignee: Motorola Solutions Inc
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Filing: 1981-10-16
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Granted: 1983-12-20
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Expires: 2001-10-16
Abstract
Abstract Circuitry for synthesizing a busy or reorder tone comprised of a first tone having a frequency of 770 Hz and a second tone having a frequency of 1150 Hz is described. The inventive synthesizing circuitry requires only one clock oscillator, whose output is coupled to a programmable divider. The programmable divider is switched between two divisor numbers at a frequency that is substantially one-half of a frequency selected from a predetermined range of frequencies substantially midway between 770 Hz and 1150 Hz. In the preferred embodiment, the programmable divider output is switched between frequencies of 1250 Hz and 883.3 Hz at a 500 Hz rate. The programmable divider output is then interrupted at a 2 Hz rate to provide the synthesized busy signal. The inventive synthesizing circuitry may be advantageously utilized in mobile or portable radios for providing a busy signal that sounds essentially identical to a fast busy or reorder tone comprised of two tones.
Inventors
- 👤 Michael F. Barnes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 08:32
CPC Classifications
H; H03; H03K; H03K23/00; H03K23/64; H03K23/66; H03K23/667
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
180 words
Circuitry for synthesizing a tone output signal that approximates a multi-frequency signal comprised of a first tone having a first predetermined frequency and a second tone having a second predetermined frequency, said synthesizing circuitry comprising: a signal source for generating a clock signal having a predetermined frequency that is greater than said first predetermined frequency and said second predetermined frequency; means for generating a control signal alternately having first and second states at a frequency that is substantially one-half of a frequency selected from a predetermined range of frequencies substantially midway between said first predetermined frequency and said second predetermined frequency; and means coupled to the clock signal source and generating means for dividing the clock signal by a first number in response to the first state of the control signal to produce the tone output signal having a first frequency greater than said first predetermined frequency and by a second number in response to the second state of the control signal to produce the tone output signal having a second frequency that is greater than said second predetermined frequency.
Claim 2
Dependent Claim
180 words
Circuitry for synthesizing a tone output signal that approximates a multi-frequency signal comprised of a first tone having a first predetermined frequency and a second tone having a second predetermined frequency, said synthesizing circuitry comprising: a signal source for generating a clock signal having a predetermined frequency that is greater than said first predetermined frequency and said second predetermined frequency; means for generating a control signal alternately having first and second states at a frequency that is substantially one-half of a frequency selected from a predetermined range of frequencies substantially midway between said first predetermined frequency and said second predetermined frequency; and means coupled to the clock signal source and generating means for dividing the clock signal by a first number in response to the first state of the control signal to produce the tone output signal having a first frequency greater than said first predetermined frequency and by a second number in response to the second state of the control signal to produce the tone output signal having a second frequency that is greater than said second predetermined frequency.
Claim 3
Dependent Claim
79 words
The synthesizing circuitry according to claim 1, further including: output signal utilization means; second means for generating a second control signal alternately having first and second states at a predetermined frequency. switching means for coupling the tone output signal to the output signal utilization means in responses to a first state of a second control signal and decoupling the tone output signal from the output signal utilization means in response to a second state of the second control signal.
Claim 4
Dependent Claim
78 words
The synthesizing circuitry according to claim 2, further adapted for use in a radio for synthesizing a busy signal, said output signal utilization means comprising a handset having a speaker and microphone coupled to the radio, said radiotelephone operable on at least one radio channel and generating a busy enable signal when the radio channel is in use by another radio, and said second generating means responsive to the busy enable signal for generating the second control signal.
Claim 5
Dependent Claim
42 words
The synthesizing circuitry according to claim 2 or 3, wherein said first tone has a frequency of 770 Hertz and said second tone has a frequency of 1150 Hertz, and wherein said range of frequencies extends from 800 Hertz to 1000 Hertz.
Claim 6
Dependent Claim
68 words
The synthesizing circuitry according to claim 4, wherein said first generating means includes second dividing means coupled to the clock signal source for dividing the clock signal by a predetermined number to provide the first control signal, and wherein said second generating means includes third dividing means coupled to the clock signal source for dividing the clock signal by a predetermined number to provide the second control signal.
Claim 7
Dependent Claim
58 words
The synthesizing circuitry according to claim 5, wherein said clock signal has a frequency of 30,000 Hertz, said first number of said first dividing means is 24, said second number of said first dividing means is 36, said predetermined number of said second dividing means is 60, and said predetermined number of said second dividing means is 250.
Claim 8
Independent Claim
168 words
A method for synthesizing a tone output signal that approximates a multi-frequency signal comprised of a first tone having a first predetermined frequency and a second tone having a second predetermined frequency, said method comprising the steps of: (a) generating a clock signal having a frequency that is greater than said first predetermined frequency and said second predetermined frequency; (b) generating a control signal alternately having first and second states at a frequency that is substantially one-half of a frequency selected from a predetermined range of frequencies substantially midway between said first predetermined frequency and said second predetermined frequency; and (c) dividing the clock signal by a first number in response to the first state of the control signal to produce the tone output signal having a first frequency greater than said first predetermined frequency and by a second number in response to the second state of the control signal to produce the tone output signal having a second frequency that is greater than said second predetermined frequency.
Claim 9
Independent Claim
168 words
A method for synthesizing a tone output signal that approximates a multi-frequency signal comprised of a first tone having a first predetermined frequency and a second tone having a second predetermined frequency, said method comprising the steps of: (a) generating a clock signal having a frequency that is greater than said first predetermined frequency and said second predetermined frequency; (b) generating a control signal alternately having first and second states at a frequency that is substantially one-half of a frequency selected from a predetermined range of frequencies substantially midway between said first predetermined frequency and said second predetermined frequency; and (c) dividing the clock signal by a first number in response to the first state of the control signal to produce the tone output signal having a first frequency greater than said first predetermined frequency and by a second number in response to the second state of the control signal to produce the tone output signal having a second frequency that is greater than said second predetermined frequency.
Claim 10
Dependent Claim
73 words
The method according to claim 7, further including the steps of: (d) generating a second control signal alternately having first and second states at a predetermined frequency; and (e) coupling the tone output signal to output signal utilization means in response to the first state of the second control signal and decoupling the tone output signal from the output signal utilization means in response to the second state of the second control signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-12-19 | 1987-06-20 | 1987-12-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-12-19 | 1991-06-20 | 1991-12-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-12-19 | 1995-06-20 | 1995-12-20 | $7700.00 | Window Closed / Lapsed |