Semiconductor current regulator and switch

Claim 3

The apparatus of claim 1 wherein said control means comprises a gate electrode of predetermined gate capacity and wherein said storage capacitance for accumulation of unidirectional pulses comprises said gate capacity.

Claim 4

The apparatus of claim 2 wherein said oscillator means further comprises an input buffer means adapted to be coupled between said oscillator means and said external signal to provide a signal compatible to said oscillator means to initiate oscillation in response to said external signal.

Claim 5

The apparatus of claim 3 wherein said converter means comprises diode means for coupling said converter means to said gate electrode.

Claim 6

The apparatus of claim 4 wherein said predetermined voltage is positive and said current conducting means comprises an NMOS transistor.

Claim 7

The apparatus of claim 5 wherein said oscillator means comprises a first NOR gate having a logic output coupled to said output for oscillatory signals and to a first terminal of a capacitor, said capacitor having a second terminal coupled to a first terminal of a first and second resistor, said first resistor having a second terminal connected to a first logic input terminal of said first NOR gate and a logic output terminal of a second NOR gate, and said second resistor having a second terminal coupled to a first logic input terminal of said second NOR gate, said second NOR gate having a second logic input terminal coupled to a power source return terminal, said first NOR gate having a second logic input terminal coupled to a drain terminal of an inverting buffer input transistor and a first terminal of a third resistor, said third resistor having a second terminal coupled to a power source input terminal, said input transistor having a source terminal coupled to said power source return terminal and a gate electrode coupled to an external signal input for controlling said oscillator, and wherein said first and second NOR gates have power supply terminals coupled to said power source input and return terminals.

Claim 8

A switching apparatus, responsive to an external signal applied to a control input terminal, for permitting electrical current flow from a power source input terminal to a load input terminal, in response to an "on" portion of said external signal and inhibiting electrical current flow in response to an "off" portion of said external signal, and having a common terminal, comprising: an enhancement mode MOS transistor having drain, source and gate electrodes, said drain and source electrodes being serially connected between said power source input terminal and said load input terminal, and said gate electrode being adapted for regulating said current flow in response to a control voltage applied to said gate electrode; driver means coupled to said power source input terminal, said gate electrode, said common terminal, and said control input terminal for generating said control voltage on said gate electrode in response to said external signal applied to said control input terminal, and wherein said control voltage, in response to said "on" portion exceeds in magnitude a voltage appearing on said power source input terminal; clamp means coupled to said gate electrode, said control input terminal, and said common terminal for discharging and holding in an off-state said gate electrode in response to said "off" portion; and buffer means coupled to said driver means, said clamp means, said power source input terminal, and said control input terminal, for receiving and interpreting said external signal to differentiate said "on" portions and "off" portions so as to energize said driver means and clamp means alternatively during said "on" portions and "off" portions respectively.

Claim 9

A switching apparatus, responsive to an external signal applied to a control input terminal, for permitting electrical current flow from a power source input terminal to a load input terminal, in response to an "on" portion of said external signal and inhibiting electrical current flow in response to an "off" portion of said external signal, and having a common terminal, comprising: an enhancement mode MOS transistor having drain, source and gate electrodes, said drain and source electrodes being serially connected between said power source input terminal and said load input terminal, and said gate electrode being adapted for regulating said current flow in response to a control voltage applied to said gate electrode; driver means coupled to said power source input terminal, said gate electrode, said common terminal, and said control input terminal for generating said control voltage on said gate electrode in response to said external signal applied to said control input terminal, and wherein said control voltage, in response to said "on" portion exceeds in magnitude a voltage appearing on said power source input terminal; clamp means coupled to said gate electrode, said control input terminal, and said common terminal for discharging and holding in an off-state said gate electrode in response to said "off" portion; and buffer means coupled to said driver means, said clamp means, said power source input terminal, and said control input terminal, for receiving and interpreting said external signal to differentiate said "on" portions and "off" portions so as to energize said driver means and clamp means alternatively during said "on" portions and "off" portions respectively.

Claim 10

The apparatus of claim 7 further comprising a stabilizer means coupled to said power source input terminal, said common terminal, said buffer means, said clamp means, and said driver means for protecting said gate electrode, said buffer, said driver, and said clamp means from voltage transients exceeding a predetermined level appearing on said power source input terminal.

Claim 11

The apparatus of claim 8 wherein said voltage appearing on said power source input terminal is positive, and said MOS transistor is an NMOS transistor.