US4417283A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital signal processing system
Assignee: Toshiba Corp
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Filing: 1981-07-14
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Granted: 1983-11-22
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Expires: 2001-07-14
Abstract
Abstract A digital signal processing system in which the actual signal data obtained through digitalization of the information signal and control data of the digital control signals are used for the control of the actual signal data and are transmitted together with a sync signal between two circuits wherein the control data are provided to at least part of an actual signal data transmission line for transmitting the various data and the control data are transmitted during the period of absence of an actual signal data on the transmission line or during the period of the sync signal.
Inventors
- 👤 Susumu Hoshimi
- 👤 Tadashi Kojima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 20:13
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/06; G11C5/066; G11B; G11B20/00; G11B20/10; G11B20/10527; G11B20/12; G11B20/1201; G11B20/1207; G11B20/1208; G11B2020/10537; G11B2020/10546; G11B2220/00; G11B2220/90
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
118 words
A circuit arrangement for processing analog audio data into a format for transmitting, receiving and playing back in a video format comprising, an analog to digital converter receiving said analog audio data, a large scale integration circuit with clock, read-write, input, output, chip select, data and address terminals, receiving the output of said analog to digital converter, a random access memory connected to said read-write, data and address terminals of said large scale integration circuit, a first tri-state buffer attached to supply outputs to certain of said data terminals of said large scale integration circuit and receiving an input from one of said chip select terminals and a first plurality of switches connected to said first tri-state buffer.
Claim 2
Dependent Claim
118 words
A circuit arrangement for processing analog audio data into a format for transmitting, receiving and playing back in a video format comprising, an analog to digital converter receiving said analog audio data, a large scale integration circuit with clock, read-write, input, output, chip select, data and address terminals, receiving the output of said analog to digital converter, a random access memory connected to said read-write, data and address terminals of said large scale integration circuit, a first tri-state buffer attached to supply outputs to certain of said data terminals of said large scale integration circuit and receiving an input from one of said chip select terminals and a first plurality of switches connected to said first tri-state buffer.
Claim 3
Dependent Claim
29 words
A circuit arrangement according to claim 1 wherein said first tri-state buffer can take a high or low state depending upon the positions of said first plurality of switches.
Claim 4
Dependent Claim
28 words
A circuit arrangement according to claim 2 wherein said first tri-state buffer can take a floating state when it receives an input from said one chip select terminal.
Claim 5
Dependent Claim
27 words
A circuit arrangement according to claim 3 including an oscillator which supplies clock inputs to said large scale integration circuit and to said analog to digital converter.
Claim 6
Dependent Claim
38 words
A circuit according to claim 4 including a second tri-state buffer connected to certain of said data terminals and a chip select terminal of said large scale integration circuit and a microcomputer connected to said second tri-state buffer.
Claim 7
Dependent Claim
75 words
A circuit according to claim 5 including a playback input terminal which receives a playback signal, a sync separator connected to said playback input terminal, a first dubbing input switch connected to said sync separator, said oscillator and to said clock terminal of said large scale integration circuit, a playback large scale integration circuit receiving an output of said sync separator and a second random access memory connected to said playback large scale integration circuit.
Claim 8
Dependent Claim
36 words
A circuit according to claim 6 including a second dubbing/input switch connected to said analog to digital converter, to said playback large scale integration circuit and to the input terminal of said large scale integration circuit.
Claim 9
Dependent Claim
36 words
A circuit according to claim 7 including a third dubbing/input switch connected to said oscillator to change the frequency of the clock signal to said large scale integration circuit for NTSC and PAL television signal formats.
Claim 10
Dependent Claim
27 words
A circuit according to claim 7 including a latch circuit connected to said playback large scale integration circuit, and a second microcomputer connected to said latch circuit.
Claim 11
Dependent Claim
30 words
A circuit according to claim 9 including a third tri-state buffer with a plurality of switches connected to said second random access memory and said playback large scale integration circuit.
Claim 12
Dependent Claim
31 words
A circuit according to claim 10 including a buffer connected to said playback large scale integration circuit to said third tri-state buffer, to said latch circuit and to said second microcomputer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-11-21 | 1987-05-23 | 1987-11-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-11-21 | 1991-05-23 | 1991-11-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-11-21 | 1995-05-23 | 1995-11-22 | $7700.00 | Window Closed / Lapsed |