US4417197A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electronic system for simultaneous control of two or more pulse modulators
Assignee: Individual
•
Filing: 1981-07-27
•
Granted: 1983-11-22
•
Expires: 2001-07-27
Abstract
Abstract Disclosed is an electronic system, that controls simultaneously two or more asynchronous pulse modulators such that the sum of all pulses is modulated as if emanating from one single source.
Inventors
- 👤 Francisc C. Schwarz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 03:12
CPC Classifications
H; H02; H02M; H02M3/00; H02M3/02; H02M3/04; H02M3/10; H02M3/145; H02M3/155; H02M3/156; H02M3/158; H02M3/1584
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
198 words
A circuit for controlling the transfer of energy from an input means to a single output, comprising in combination: a first pulse generator for transferring electrical energy from the input means to the output; a second pulse generator for transferring electrical energy from the input means to the output; first input signal means connected to said first pulse generator to produce a first input pulse to said first pulse generator; second input signal means connected to said second pulse generator to provide a second input pulse to said second pulse generator; said first and second input signal means sequentially energizing said first and second pulse generators to sequentially transfer electrical energy from the input means to the output; reference signal means for providing a reference signal; comparator means for comparing the output of said first and second pulse generators to the reference signal from said reference signal means; and gate means connected to said first and second input signal means for changing the next input pulse to one of said first and second pulse generators in accordance with the difference between said reference signal and the previous output of the other of said first and second pulse generators.
Claim 2
Dependent Claim
198 words
A circuit for controlling the transfer of energy from an input means to a single output, comprising in combination: a first pulse generator for transferring electrical energy from the input means to the output; a second pulse generator for transferring electrical energy from the input means to the output; first input signal means connected to said first pulse generator to produce a first input pulse to said first pulse generator; second input signal means connected to said second pulse generator to provide a second input pulse to said second pulse generator; said first and second input signal means sequentially energizing said first and second pulse generators to sequentially transfer electrical energy from the input means to the output; reference signal means for providing a reference signal; comparator means for comparing the output of said first and second pulse generators to the reference signal from said reference signal means; and gate means connected to said first and second input signal means for changing the next input pulse to one of said first and second pulse generators in accordance with the difference between said reference signal and the previous output of the other of said first and second pulse generators.
Claim 3
Dependent Claim
19 words
A circuit as set forth in claim 1, wherein said first and second pulse generator comprise power switch means.
Claim 4
Dependent Claim
39 words
A circuit as set forth in claim 1, wherein said first and second input signal means includes a clock for generating clock pulses; and means connecting said clock pulses for sequentially activating said first and second input signal means.
Claim 5
Dependent Claim
57 words
A circuit as set forth in claim 3, wherein said comparator means comprises an integrator means for integrating the output of said first and second pulse generators; and a discriminator for discriminating between the output of said integrator means and a detection level to provide a discriminating output upon a desired output level of said integration means.
Claim 6
Dependent Claim
44 words
A circuit as set forth in claim 4, wherein said gate means includes a gate connected to first and second signal input means for sequentially deactivating the output of said first and second signal input means in accordance with the output of said discriminator.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-11-21 | 1987-05-23 | 1987-11-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-11-21 | 1991-05-23 | 1991-11-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-11-21 | 1995-05-23 | 1995-11-22 | $7700.00 | Window Closed / Lapsed |