US4416177A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data input for computer organ
Assignee: Individual
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Filing: 1981-03-02
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Granted: 1983-11-22
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Expires: 2001-03-02
Abstract
Abstract Computer organ tone input for alterable stops is achieved by single-key input through a decoded keyboard which is couple to a logic network and optoelectrical output drive circuitry. The decoder circuitry activates selected optical emitters in an array which is mounted in the optical reader of a computer organ such that the decoder circuitry is electronically isolated from the computer organ. The invention eliminates the need for a tone card library, does not interfere with the sensitive circuitry of the organ and permits instantaneous reprogramming of alterable voices.
Inventors
- 👤 Marvin Loeb
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 23:02
CPC Classifications
G; G10; G10H; G10H1/00; G10H1/18; G10H1/24; G10H7/00; G10H7/002
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
231 words
In combination a digital computer organ equipped with an optical card reader having a number of optical sensors in a pattern and operable for altering the contents of a number of voice patterns of the organ; a keyboard with a plurality of keys, a first group of keys of the keyboard being specific to selected voice patterns of said computer organ, and a second group of keys of the keyboard being function keys for modification of a selected voice pattern, said keyboard being operative to generate a binary signal to indicate actuation of individual keys of the keyboard; a decoder responsive to said binary signal for generating a unique digital word identifying a selected voice pattern; a storage register for temporarily storing said digital word from said decoder; a circuit means responsive to said stored word in said storage register for generating a plurality of digital bytes in a preselected sequence; a number of optoelectrical emitters adjacent to and arranged in an array matching the pattern of said optical sensors of said optical card reader of said digital computer organ; and a number of drivers coupled to said optoelectrical emitters and responsive to said sequence of bytes for driving corresponding optoelectrical emitters such that signals applied to said emitters are recognizable at corresponding optical sensors of the organ as a programming pattern for alterable voice patterns of said digital computer organ.
Claim 2
Dependent Claim
231 words
In combination a digital computer organ equipped with an optical card reader having a number of optical sensors in a pattern and operable for altering the contents of a number of voice patterns of the organ; a keyboard with a plurality of keys, a first group of keys of the keyboard being specific to selected voice patterns of said computer organ, and a second group of keys of the keyboard being function keys for modification of a selected voice pattern, said keyboard being operative to generate a binary signal to indicate actuation of individual keys of the keyboard; a decoder responsive to said binary signal for generating a unique digital word identifying a selected voice pattern; a storage register for temporarily storing said digital word from said decoder; a circuit means responsive to said stored word in said storage register for generating a plurality of digital bytes in a preselected sequence; a number of optoelectrical emitters adjacent to and arranged in an array matching the pattern of said optical sensors of said optical card reader of said digital computer organ; and a number of drivers coupled to said optoelectrical emitters and responsive to said sequence of bytes for driving corresponding optoelectrical emitters such that signals applied to said emitters are recognizable at corresponding optical sensors of the organ as a programming pattern for alterable voice patterns of said digital computer organ.
Claim 3
Dependent Claim
194 words
An apparatus according to claim 1 wherein said byte generating circuit means comprises: memory address and control logic circuit means coupled to receive the output of said storage register and for supplying address information to a digital memory means; a digital memory means having randomly addressable storage registers, said memory means being coupled to receive the output of said memory address and control logic means for supplying a sequence of parallel data bit signals to a parallel output register in response to an input address, said digital memory means including read only memory means and random access memory means; a parallel output register coupled to receive data output of said digital memory means, said output register having parallel outputs coupled to said drivers; and means for generating a gated signal coupled to said memory address and control logic circuit means for providing a signal to said memory address and control logic, in order to increment addresses of said read only memory means, said read only memory means being structured to contain preselected digital data specifying selected samples of at least one synthesized waveform which are intelligible by a computer within said digital computer organ.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-11-21 | 1987-05-23 | 1987-11-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-11-21 | 1991-05-23 | 1991-11-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-11-21 | 1995-05-23 | 1995-11-22 | $7700.00 | Window Closed / Lapsed |