Intrinsic barrier

Claim 2

An intrinsic barrier comprising: a first and second input lines for receiving input from an electrical source, a first and second output lines for electrically connecting electronic circuitry that exists in a potentially explosive environment, said second input line and said second output line forming a common lead, a transistor having collector, base and emitter leads, a fuse electrically connected between said first input line and the collector lead of said transistor, a first zener diode interconnecting the base lead of said transistor and said common lead, a first resistor electrically series connected in said first output line, a voltage limiting means electrically interposed between the emitter lead of said transistor and said common lead; said voltage limiting means also being electrically interposed between said first output line and the emitter lead of said transistor, said transistor and said first zener diode combining to function as a regulated voltage source to said first and said second output lines, said first resistor being selected to limit the current in said first and said second output lines to a preselected maximum, said voltage limiting means limiting the output voltage on said first and said second output lines only in the event that said first zener diode opens or a short occurs between the collector and the emitter leads of said transistor.

Claim 3

The intrinsic barrier defined in claim 1 wherein said voltage limiting means comprises: a second zener diode electrically connecting the emitter lead of said transistor and said common lead, a third zener diode electrically connected at one end thereof to both the emitter lead of said transistor and said first output line and electrically connected at the other end thereof to said common lead to form a redundant voltage limiter.

Claim 4

The intrinsic barrier defined in claim 2 wherein the voltage rating of said second zener diode is substantially equal to the voltage rating of said first zener diode and said third zener diode has a voltage rating slightly higher than the voltage rating of said second zener diode.

Claim 5

The intrinsic barrier defined in claim 3 wherein said fuse has a blow time under prescribed test conditions which is significantly shorter than the destruction times of said second and said third zener diodes under the same prescribed test conditions.

Claim 6

The intrinsic barrier defined in claim 1 wherein said voltage limiting means comprises: a second zener diode electrically connected at one end thereof between the emitter lead of said transistor and said first output line and at the other end thereof to said common lead.

Claim 7

An intrinsic barrier comprising: a first and second input lines for receiving input from an electrical source, a first and second output lines for electrically connecting electronic circuitry that is to receive a preselected maximum level of energy, said second input line and said second output line forming a common lead, a transistor having collector, base and emitter leads, a fuse electrically connected between said first input line and the collector lead of said transistor, a first zener diode interconnecting the base lead of said transistor and said common lead, a second zener diode electrically connecting the emitter lead of said transistor and said common lead, a third zener diode electrically connected at one end thereof to both the emitter lead of said transistor and said first output line and being electrically connected at the other end thereof to said common lead, a first resistor electrically series connected in said first output line, said transistor and said first zener diode combining to function as a regulated voltage source to said first and said second output lines; said first resistor being selected to limit the current in said first and said second output lines to a preselected maximum, said second and said third zener diodes combining to limit the output voltage on said first and said second output lines in the event that said first zener diode opens or a short occurs between the collector and emitter leads of said transistor.

Claim 8

An intrinsic barrier comprising: a first and second input lines for receiving input from an electrical source, a first and second output lines for electrically connecting electronic circuitry that is to receive a preselected maximum level of energy, said second input line and said second output line forming a common lead, a transistor having collector, base and emitter leads, a fuse electrically connected between said first input line and the collector lead of said transistor, a first zener diode interconnecting the base lead of said transistor and said common lead, a second zener diode electrically connecting the emitter lead of said transistor and said common lead, a third zener diode electrically connected at one end thereof to both the emitter lead of said transistor and said first output line and being electrically connected at the other end thereof to said common lead, a first resistor electrically series connected in said first output line, said transistor and said first zener diode combining to function as a regulated voltage source to said first and said second output lines; said first resistor being selected to limit the current in said first and said second output lines to a preselected maximum, said second and said third zener diodes combining to limit the output voltage on said first and said second output lines in the event that said first zener diode opens or a short occurs between the collector and emitter leads of said transistor.

Claim 9

An intrinsic barrier defined in claim 6 wherein: the voltage rating of said second zener diode is substantially equal to the voltage rating of the said first zener diode and said third zener diode has a voltage rating slightly higher than the voltage rating of said second zener diode.

Claim 10

An intrinsic barrier defined in claim 7 wherein: said fuse has a blow time under prescribed test conditions which is significantly shorter than the destruction times of said second and said third zener diodes under the same prescribed test conditions.

Claim 11

An intrinsic barrier defined in claim 6 which further comprises: a blocking diode electrically interconnected between said second and said third zener diodes, said blocking diode also being electrically interconnected between said first output line and the emitter lead of said transistor.

Claim 12

An intrinsic barrier defined in claim 9 which further comprises: a separate test output line having a second resistor therein, said second resistor having a resistance which is substantially larger than the resistance of said first resistor in said first output line, said test output line being connected to the emitter lead of said pass transistor and to said second zener diode whereby individual test voltages can be applied to said second and said third zener diodes.

Claim 13

An intrinsic barrier made up of two barriers stacked and encapsulated, each barrier comprising: a first and second input lines for receiving input from an electrical source, a first and second output lines for electrically connecting electronic circuitry that is to be protected, said second input line and said second output line forming a common lead, a transistor having collector base and emitter leads, a fuse electrically connected between said first input line and the collector lead of said transistor, a first zener diode interconnecting the base lead of said transistor and said common lead, a second zener diode electrically connecting the emitter lead of said transmitter and said common lead, a third zener diode electrically connected at one end thereof to both the emitter lead of said transistor a resistor electrically series connected in said first output line, and said first output line and being electrically connected at the other end thereof to said common lead, said transistor and said first zener diode combining to function as a regulated voltage source to said first and said second output lines; said second and said third zener diodes combining to limit the output voltage on said first and said second output lines in the event that said first zener diode opens or a short occurs between the collector and emitter leads of said transistor, said resistor being selected to limit the current in said first and said second output lines to a preselected maximum.

Claim 14

An intrinsic barrier made up of two barriers stacked and encapsulated, each barrier comprising: a first and second input lines for receiving input from an electrical source, a first and second output lines for electrically connecting electronic circuitry that is to be protected, said second input line and said second output line forming a common lead, a transistor having collector base and emitter leads, a fuse electrically connected between said first input line and the collector lead of said transistor, a first zener diode interconnecting the base lead of said transistor and said common lead, a second zener diode electrically connecting the emitter lead of said transmitter and said common lead, a third zener diode electrically connected at one end thereof to both the emitter lead of said transistor a resistor electrically series connected in said first output line, and said first output line and being electrically connected at the other end thereof to said common lead, said transistor and said first zener diode combining to function as a regulated voltage source to said first and said second output lines; said second and said third zener diodes combining to limit the output voltage on said first and said second output lines in the event that said first zener diode opens or a short occurs between the collector and emitter leads of said transistor, said resistor being selected to limit the current in said first and said second output lines to a preselected maximum.