US4412251A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Flicker preventing circuit
Assignee: Sony Corp
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Filing: 1981-08-31
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Granted: 1983-10-25
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Expires: 2001-08-31
Abstract
Abstract A flicker preventing circuit for a television receiver is disclosed which includes a first delay line for delaying an input video signal by one horizontal sweep period and producing a first delayed signal, a second delay line for delaying the input video signal by two horizontal periods and producing a second delayed signal, a switching circuit for selecting either the input video signal or the second delayed signal, the switching circuit being switched alternately according to which of the even and odd interlaced fields, respectively, is being displayed, an adder for adding the output signal from the switching circuit and the first delayed signal each other, and a level changing circuit for changing the level of either the input video signal or the second delayed signal relative to the level of the first delayed signal.
Inventors
- 👤 Yutaka Tanaka
- 👤 Toshinobu Isobe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 20:16
CPC Classifications
H; H04; H04N; H04N7/00; H04N7/01; H04N7/0127; H04N7/0132; G; G09; G09G; G09G1/00; G09G1/06; G09G1/14; G09G1/146; Y; Y10; Y10S; Y10S348/00; Y10S348/91
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
178 words
A flicker preventing circuit for a television receiver which displays interlaced even and odd video fields during successive field periods in response to an input video signal, each of said fields comprising a plurality of horizontal lines displayed during successive horizontal periods, said circuit comprising: delay means receiving said input video signal and providing therefrom first and second delayed signals which are delayed by one horizontal period and by two horizontal periods, respectively, relative to said input video signal; processing means receiving said input video signal and said first and second delayed signals and including means for alternatively delivering said input video signal and said second delayed signal during successive field periods, as a first output of said processing means, and delivering said first delayed signal as a second output of said processing means, with the level of said first output being different from the level of said second output; and adding means for adding said first and second outputs of said processing means and providing a corresponding sum signal as the output of said flicker preventing circuit.
Claim 2
Dependent Claim
178 words
A flicker preventing circuit for a television receiver which displays interlaced even and odd video fields during successive field periods in response to an input video signal, each of said fields comprising a plurality of horizontal lines displayed during successive horizontal periods, said circuit comprising: delay means receiving said input video signal and providing therefrom first and second delayed signals which are delayed by one horizontal period and by two horizontal periods, respectively, relative to said input video signal; processing means receiving said input video signal and said first and second delayed signals and including means for alternatively delivering said input video signal and said second delayed signal during successive field periods, as a first output of said processing means, and delivering said first delayed signal as a second output of said processing means, with the level of said first output being different from the level of said second output; and adding means for adding said first and second outputs of said processing means and providing a corresponding sum signal as the output of said flicker preventing circuit.
Claim 3
Dependent Claim
62 words
A flicker preventing circuit as in claim 1; wherein said delay means includes first delay means receiving said input video signal and delaying said input video signal by one horizontal period for providing said first delayed signal, and second delay means receiving said input video signal and delaying said input video signal by two horizontal periods for providing said second delayed signal.
Claim 4
Dependent Claim
89 words
A flicker preventing circuit as in claim 2; wherein said processing means includes switching means receiving said input video signal and said second delayed signal and being changed over during successive field periods for alternately selecting said input video signal and said second delayed signal as its output, and level changing means receiving said output of said switching means and changing a level thereof relative to a level of said first delayed signal, with the output of said level changing means being said first output of said processing means.
Claim 5
Dependent Claim
59 words
A flicker preventing circuit as in claim 1; wherein said delay means includes first delay means receiving said input video signal and delaying the latter by one horizontal period for providing said first delayed signal, and second delay means receiving said first delayed signal and further delaying the latter by one horizontal period for providing said second delayed signal.
Claim 6
Dependent Claim
96 words
A flicker preventing circuit as in claim 4; wherein said processing means includes first level changing means receiving said input video signal and providing a corresponding output with a level thereof changed relative to a level of said first delayed signal, second level changing means receiving said second delayed signal and providing a corresponding output with a level thereof changed relative to a level of said first delayed signal, and switching means selecting said outputs of said first and second level changing means alternately during successive field periods as said first output of said processing means.
Claim 7
Dependent Claim
97 words
A flicker preventing circuit as in cliam 4; wherein said processing means includes switching means receiving said input video signal and said second delayed signal and being changed over during successive field periods for alternately selecting said input video signal and said second delayed signal as said first output of said processing means, and level changing means receiving said first delayed signal and changing a level thereof relative to a level of said input video signal and said second delayed signal, with the output of said level changing means being said second output of said processing means.
Claim 8
Dependent Claim
97 words
A flicker preventing circuit as in cliam 4; wherein said processing means includes switching means receiving said input video signal and said second delayed signal and being changed over during successive field periods for alternately selecting said input video signal and said second delayed signal as said first output of said processing means, and level changing means receiving said first delayed signal and changing a level thereof relative to a level of said input video signal and said second delayed signal, with the output of said level changing means being said second output of said processing means.
Claim 9
Dependent Claim
92 words
A flicker preventing circuit as in claim 4; wherein said processing means includes switching means receiving said input video signal and said second delayed signal and changed over during successive field periods for alternately selecting said input video signal and said second delayed signal as the output of said switching means, and level changing means receiving said output of the switching means and changing a level thereof relative to a level of said first delayed signal, with the output of said level changing means being said first output of said processing means.
References Cited (Backward Citations)
US4300162A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-10-24 | 1987-04-25 | 1987-10-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-10-24 | 1991-04-25 | 1991-10-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-10-24 | 1995-04-25 | 1995-10-25 | $7700.00 | Window Closed / Lapsed |