Digital induction logging tool including a floating point A/D

Claim 2

A floating point analog-to-digital convertor for converting an input analog signal into floating point digital signals, each digital signal having a digital code representative of the exponent of a floating point number and a digital code representative of its magnitude, the convertor comprising: (a) a voltage-to-frequency convertor for generating a digital clocking signal having a frequency proportional to the magnitude of the input analog signal; (b) a comparator for generating a count direction control signal according to the instantaneous polarity of the analog input signal; (c) an up-down counter responsive to the count direction control signal for counting up or counting down in response to clock pulses generating means of the digital clocking signal during a predetermined time period; (d) a shift register having a bit position for each bit of said up-down counter and responsive to shift pulses for storing and shifting at the end of each predetermined time period the count from said up/down counter one bit position for each shift pulse in a direction to obtain a predetermined magnitude for the count contained in a predetermined sub-set number of output bits of said shift register, the set of bits having a sign bit and a most significant bit (MSB), the sub-set of shift register output bits forming the magnitude of the floating point digital sample; and (e) a shift pulse counter for counting the number of shift pulses applied to said shift register, the count in said shift pulse counter forming the exponent of the floating point digital signal.

Claim 3

The convertor of claim 1 further including means responsive to said shift register and said shift pulse counter for generating the shift pulses to said shift register until the first to occur of either the magnitude of the digital signal reaching a predetermined value or the count in said shift pulse counter reaching a predetermined count.

Claim 4

The convertor of claim 2 wherein the predetermined magnitude value is either a logic 1 or a logic 0 in the MSB when the sign bit is either positive or negative, respectively.

Claim 5

The convertor of claim 3 wherein said shift register is shifted one additional time after reaching the predetermined magnitude value.

Claim 6

The convertor of claims 2, 3 or 4 wherein said shift pulse generating means includes means for generating each predetermined time period and for transferring the count in said up-down counter into said shift register at the end of each predetermined time period.

Claim 7

A floating point analog-to-digital convertor for converting an input analog signal into a floating point digital signal having a digital code representative of the exponent of a floating point number and a digital code representative of its magnitude, the convertor comprising: (a) a voltage-to-frequency convertor for generating a digital clocking signal having a frequency proportional to the amplitude of the input analog signal; (b) a first counter for counting clock pulses of the digital clocking signal during a predetermined time period, the count in said first counter at the end of each time period representing the average value of the analog input signal taken over that time period; (c) a shaft register having a bit position for each bit of said first counter and responsive to shift pulses generating means for storing and shifting at the end of each predetermined time period one bit position for each shift pulse the count from said first counter in a direction to obtain a predetermined magnitude for the count contained in a predetermined sub-set number of output bits of said shift register, said set of bits having a sign bit and a most significant bit (MSB), the sub-set of shift register output bits forming the magnitude of the floating point digital signal; and (d) a second counter for counting the number of shift pulses applied to said shift register, the count in said shift pulse counter forming the exponent of the floating point digital sample.

Claim 8

A floating point analog-to-digital convertor for converting an input analog signal into a floating point digital signal having a digital code representative of the exponent of a floating point number and a digital code representative of its magnitude, the convertor comprising: (a) a voltage-to-frequency convertor for generating a digital clocking signal having a frequency proportional to the amplitude of the input analog signal; (b) a first counter for counting clock pulses of the digital clocking signal during a predetermined time period, the count in said first counter at the end of each time period representing the average value of the analog input signal taken over that time period; (c) a shaft register having a bit position for each bit of said first counter and responsive to shift pulses generating means for storing and shifting at the end of each predetermined time period one bit position for each shift pulse the count from said first counter in a direction to obtain a predetermined magnitude for the count contained in a predetermined sub-set number of output bits of said shift register, said set of bits having a sign bit and a most significant bit (MSB), the sub-set of shift register output bits forming the magnitude of the floating point digital signal; and (d) a second counter for counting the number of shift pulses applied to said shift register, the count in said shift pulse counter forming the exponent of the floating point digital sample.

Claim 9

The convertor of claim 6 further including means responsive to said shift register and said second counter for generating the shift pulses to said shift register until the first to occur of either the magnitude of the digital signal reaching a predetermined value or the count in said second counter reaching a predetermined count.

Claim 10

The convertor of claim 7 wherein the predetermined magnitude value is a logic 1 in the MSB.

Claim 11

The convertor of claim 8 wherein said shift register is shifted one additional time after reaching the predetermined magnitude value.

Claim 12

The convertor of claims 7, 8 or 9 wherein said shift pulse generating means includes means for generating each predetermined time period, and for transferring the count in said first counter into said shift register at the end of each predetermined time period.

Claim 13

A bi-polar floating point analog-to-digital convertor for obtaining bi-polar digital signals in a digital induction logging tool which includes a transmitter coil which responds to a transmitter signal to induce eddy currents to flow in sub-surface formations and a receiver coil which generates a formation characteristic signal in response to the presence of these currents, the tool measuring a component of the characteristic signal in a phase sensitive detector in response to a reference phase signal having the same phase as the component signal to be detected, said convertor generating floating point digital signals representative of the detected component signals, each digital signal having a digital code representative of the exponent of a floating point number and a digital code representative of its magnitude, the convertor comprising: (a) a bi-polar voltage-to-frequency convertor responsive to the detected component signals from said phase sensitive detector for generating a digital clocking frequency signal having a frequency proportional to the magnitude of the detected component signal; (b) a polarity sensing means responsive to the detected component signal for generating a count direction control signal according to the polarity of the detected component signal; (c) an up-down counter responsive to the count direction control signal for counting clock cycles of the digital frequency signal during a predetermined time period, the count in said up-down counter representing the average value of the detected component signal; (d) a shift register having a stage for each bit of said up-down counter and responsive to shift pulses generating means for storing and shifting at the end of each predetermined time period the count from said up-down counter in a direction to increase the magnitude of the count contained in a predetermined sub-set number of output bits of said shift register, said set of bits having a sign bit and a most significant bit (MSB), the sub-set of shift register output bits forming the magnitude of the floating point digital sample; and (e) a shift pulse counter for counting the number of shift pulses applied to said shift register, said shift register shifting its stored count one bit position for each shift pulse until the first to occur of either the magnitude of the digital signal reaching a predetermined threshold value or the count in said shift pulse counter reaching a predetermined count, the count in said shift pulse counter forming the exponent of the floating point digital sample.

Claim 14

A bi-polar floating point analog-to-digital convertor for obtaining bi-polar digital signals in a digital induction logging tool which includes a transmitter coil which responds to a transmitter signal to induce eddy currents to flow in sub-surface formations and a receiver coil which generates a formation characteristic signal in response to the presence of these currents, the tool measuring a component of the characteristic signal in a phase sensitive detector in response to a reference phase signal having the same phase as the component signal to be detected, said convertor generating floating point digital signals representative of the detected component signals, each digital signal having a digital code representative of the exponent of a floating point number and a digital code representative of its magnitude, the convertor comprising: (a) a bi-polar voltage-to-frequency convertor responsive to the detected component signals from said phase sensitive detector for generating a digital clocking frequency signal having a frequency proportional to the magnitude of the detected component signal; (b) a polarity sensing means responsive to the detected component signal for generating a count direction control signal according to the polarity of the detected component signal; (c) an up-down counter responsive to the count direction control signal for counting clock cycles of the digital frequency signal during a predetermined time period, the count in said up-down counter representing the average value of the detected component signal; (d) a shift register having a stage for each bit of said up-down counter and responsive to shift pulses generating means for storing and shifting at the end of each predetermined time period the count from said up-down counter in a direction to increase the magnitude of the count contained in a predetermined sub-set number of output bits of said shift register, said set of bits having a sign bit and a most significant bit (MSB), the sub-set of shift register output bits forming the magnitude of the floating point digital sample; and (e) a shift pulse counter for counting the number of shift pulses applied to said shift register, said shift register shifting its stored count one bit position for each shift pulse until the first to occur of either the magnitude of the digital signal reaching a predetermined threshold value or the count in said shift pulse counter reaching a predetermined count, the count in said shift pulse counter forming the exponent of the floating point digital sample.

Claim 15

The convertor of claim 11 wherein the predetermined threshold value is either a logic 1 or a logic 0 in the MSB of the sub-set of shift register bits if the sign bit is positive or negative, respectively.

Claim 16

The convertor of claim 12 wherein said shift register is shifted one additional time after reaching the predetermined threshold magnitude value.

Claim 17

The convertor of claim 11 wherein the proportionality constant of said bi-polar voltage-to-frequency convertor and the predetermined time interval establish the relationship between the digital signal code and the integrated value of the component signal.

Claim 18

The convertor of claim 11 wherein the predetermined count in said shift pulse counter is zero.

Claim 19

The convertor of claim 11 wherein the polarity sensing means is an analog comparator.

Claim 20

A floating point analog-to-digital convertor for use in a digital induction logging tool that includes a transmitter coil which responds to a transmitter signal to induce eddy currents to flow in sub-surface formations and a receiver coil which generates a formation characteristic signal in response to the presence of these currents, the tool measuring a component of the characteristic signal in a phase sensitive detector in response to a reference phase signal having the same phase as the component signal to be detected, said convertor obtaining floating point digital signals representative of the detected component signals, each digital sample having a digital code representative of the exponent of a floating point number and a digital code representative of its magnitude, the converter comprising: (a) a voltage-to-frequency convertor responsive to the detected component signals from said phase sensitive detector for generating a digital clocking frequency signal having a frequency proportional to the amplitude of the detected component signal; (b) a first counter for counting clock cycles of the digital frequency signal during a predetermined time period, the count in said first counter at the end of each time period representing the average value of the detected component signal taken over the predetermined time period; (c) a shift register having a stage for each bit of said first counter and responsive to shift pulses for storing and shifting at the end of each predetermined time period the count from said first counter in a direction to increase the magnitude of the count contained in a predetermined sub-set number of output bits of said shift register, said set of bits having a most significant a direction to increase the magnitude of the count contained in a predetermined sub-set number of output bits of said shift register, said set of bits having a most significant bit (MSB), the sub-set of shift register output bits forming the magnitude of the floating point digital sample; and (d) a second counter for counting the number of shift pulses applied to said shift register, said shift register shifting its stored count one bit position for each shift pulse until the first to occur of either the magnitude of the digital sample reaching a predetermined threshold value or the count in said second counter reaching a predetermined count, the count in said second counter forming the exponent of the floating point conversion sample.

Claim 21

A floating point analog-to-digital convertor for use in a digital induction logging tool that includes a transmitter coil which responds to a transmitter signal to induce eddy currents to flow in sub-surface formations and a receiver coil which generates a formation characteristic signal in response to the presence of these currents, the tool measuring a component of the characteristic signal in a phase sensitive detector in response to a reference phase signal having the same phase as the component signal to be detected, said convertor obtaining floating point digital signals representative of the detected component signals, each digital sample having a digital code representative of the exponent of a floating point number and a digital code representative of its magnitude, the converter comprising: (a) a voltage-to-frequency convertor responsive to the detected component signals from said phase sensitive detector for generating a digital clocking frequency signal having a frequency proportional to the amplitude of the detected component signal; (b) a first counter for counting clock cycles of the digital frequency signal during a predetermined time period, the count in said first counter at the end of each time period representing the average value of the detected component signal taken over the predetermined time period; (c) a shift register having a stage for each bit of said first counter and responsive to shift pulses for storing and shifting at the end of each predetermined time period the count from said first counter in a direction to increase the magnitude of the count contained in a predetermined sub-set number of output bits of said shift register, said set of bits having a most significant a direction to increase the magnitude of the count contained in a predetermined sub-set number of output bits of said shift register, said set of bits having a most significant bit (MSB), the sub-set of shift register output bits forming the magnitude of the floating point digital sample; and (d) a second counter for counting the number of shift pulses applied to said shift register, said shift register shifting its stored count one bit position for each shift pulse until the first to occur of either the magnitude of the digital sample reaching a predetermined threshold value or the count in said second counter reaching a predetermined count, the count in said second counter forming the exponent of the floating point conversion sample.

Claim 22

The convertor of claim 17 wherein the predetermined threshold value is a logic 1 in the MSB of the sub-set of shift register bits.

Claim 23

The convertor of claim 17 wherein the proportionality constant of said voltage-to-frequency convertor and the predetermined time interval determine the relationship between the digital signal code and the magnitude of the component signal converted.

Claim 24

The convertor of claim 17 wherein the predetermined count in said second counter is zero.

Claim 25

The convertor of claim 18 wherein said shift register is shifted one additional time after reaching the predetermined threshold magnitude value.

Claim 28

The method of claim 22 further including the step of generating the shift pulses to said shift register until the first to occur of either the magnitude of the digital signal reaching a predetermined value or the count in said shift register reaching a predetermined count.

Claim 29

The method of claim 23 wherein said shift register is shifted one additional time after reaching the predetermined magnitude value.