US4412099A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Sound synthesizing apparatus
Assignee: Panasonic Holdings Corp
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Filing: 1981-05-15
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Granted: 1983-10-25
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Expires: 2001-05-15
Abstract
Abstract In this speech synthesizer which announces the time, storage and complexity is minimized by switching selection of fixed data and variable data from corresponding memories, to compose the phrase "the time is five o'clock".
Inventors
- 👤 Katsuyuki Niyada
- 👤 Taisuke Watanabe
- 👤 Shoji Hiraoka
- 👤 Shuji Morii
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 16:22
CPC Classifications
H; H04; H04M; H04M1/00; H04M1/64; H04M1/65; H04M1/6505; H04M1/651; G; G04; G04G; G04G13/00; G10; G10L; G10L19/00
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
253 words
A sound synthesizing apparatus comprising: (a) a sound synthesizing circuit for converting various parameters indicative of sound data into sound signals; (b) a timing control circuit for producing various timing signals in accordance with an external synchronous signal, a signal from said sound synthesizing circuit and with an external trigger signal; (c) a sequence control circuit responsive to a signal indicative of termination of one word from said sound synthesizing circuit, for generating an output signal; (d) a first memory in which information indicative of the order of words to be pronounced and intervals between said words as well as switching information are prestored, the address of said first memory being designated by said output signal of said sequence control circuit; (e) a variable data producing circuit for producing data which varies as a function of time; (f) a switching circuit controlled by said switching information for selecting said information indicative of the order of words from said first memory or the variable data; (g) a second memory in which pieces of information indicative of first addresses of sound data are prestored, one of said pieces of information being selected in accordance with said information or variable data from said switching circuit; and (h) a third memory in which said sound data is prestored as parameters, said sound data being read out in accordance with said information from said second memory one after another in synchronism with a timing signal from said timing control circuit and a signal from said sound synthesizing circuit.
Claim 2
Dependent Claim
253 words
A sound synthesizing apparatus comprising: (a) a sound synthesizing circuit for converting various parameters indicative of sound data into sound signals; (b) a timing control circuit for producing various timing signals in accordance with an external synchronous signal, a signal from said sound synthesizing circuit and with an external trigger signal; (c) a sequence control circuit responsive to a signal indicative of termination of one word from said sound synthesizing circuit, for generating an output signal; (d) a first memory in which information indicative of the order of words to be pronounced and intervals between said words as well as switching information are prestored, the address of said first memory being designated by said output signal of said sequence control circuit; (e) a variable data producing circuit for producing data which varies as a function of time; (f) a switching circuit controlled by said switching information for selecting said information indicative of the order of words from said first memory or the variable data; (g) a second memory in which pieces of information indicative of first addresses of sound data are prestored, one of said pieces of information being selected in accordance with said information or variable data from said switching circuit; and (h) a third memory in which said sound data is prestored as parameters, said sound data being read out in accordance with said information from said second memory one after another in synchronism with a timing signal from said timing control circuit and a signal from said sound synthesizing circuit.
Claim 3
Dependent Claim
213 words
A sound synthesizing apparatus comprising a sound synthesizing circuit, which converts sound data into sound signals, and a control circuit, said control circuit comprising: (a) a first memory in which information indicative of the order of words to be pronounced and intervals between said words as well as switching information are prestored, said first memory being arranged to send a piece of address information one after another in response to a timing signal fed thereto; (b) a variable data producing circuit for producing data which varies as a function of time; (c) a switching circuit controlled by said switching information for selecting said information indicative of the order of words from said first memory or the variable data; (d) a second memory in which pieces of information indicative of first addresses of sound data are prestored, one of said pieces of information being selected in accordance with said information or variable data from said switching circuit; and (e) a third memory in which said sound data is prestored as parameters, said sound data being read out in accordance with said information from said second memory one after another in synchroniusm with an external synchronous signal, the read out parameter train being fed to said sound synthesizing circuit to be converted into sound signals.
Claim 4
Dependent Claim
213 words
A sound synthesizing apparatus comprising a sound synthesizing circuit, which converts sound data into sound signals, and a control circuit, said control circuit comprising: (a) a first memory in which information indicative of the order of words to be pronounced and intervals between said words as well as switching information are prestored, said first memory being arranged to send a piece of address information one after another in response to a timing signal fed thereto; (b) a variable data producing circuit for producing data which varies as a function of time; (c) a switching circuit controlled by said switching information for selecting said information indicative of the order of words from said first memory or the variable data; (d) a second memory in which pieces of information indicative of first addresses of sound data are prestored, one of said pieces of information being selected in accordance with said information or variable data from said switching circuit; and (e) a third memory in which said sound data is prestored as parameters, said sound data being read out in accordance with said information from said second memory one after another in synchroniusm with an external synchronous signal, the read out parameter train being fed to said sound synthesizing circuit to be converted into sound signals.
Claim 5
Dependent Claim
27 words
A sound synthesizing apparatus as claimed in claim 2, further comprising a decoder responsive to said output information from said first memory for detecting a termination signal.
Claim 6
Dependent Claim
33 words
A sound synthesizing apparatus as claimed in claim 2, wherein said second memory comprises a latch controlled by an external synchronous signal and a memory responsive to the output data of said latch.
Claim 7
Dependent Claim
78 words
A sound synthesizing apparatus as claimed in claim 2, wherein said third memory comprises: (a) a latch counter responsive to said information from said second memory; (b) a memory responsive to the output data from said latch counter; (c) a shift register responsive to the output data of said memory; and (d) means for controlling said latch counter and said shift register in accordance with external synchronous signals and with a request signal from said sound synthesizing circuit.
Claim 8
Dependent Claim
47 words
A sound synthesizing apparatus as claimed in claim 2, further comprising a sequence control circuit, said sequence control circuit having gate circuits responsive to external synchronous signal and to a signal, which is manually produced, and a latch counter responsive to output signals of said gate circuits.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-10-24 | 1987-04-25 | 1987-10-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-10-24 | 1991-04-25 | 1991-10-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-10-24 | 1995-04-25 | 1995-10-25 | $7700.00 | Window Closed / Lapsed |