Notched cell ROM

Claim 2

A serial access MOS ROM comprised of: a semiconductor substrate of a first conductivity type; a plurality of buried regions formed in said substrate serving as bit lines of an opposite conductivity type; a layer of electrical insulating material covering said bit lines; a plurality of conductive paths serving as word lines lying substantially perpendicular above said bit lines and separated from said bit lines by said insulating material; a plurality of semiconductor memory cells formed at each cross-over of said bit lines and said word lines, said plurality of conductive paths having narrowed width portions at selected ones of said cross-overs; and wherein said word lines serve as a mask during the formation of said bit lines and the width of each of said word lines at each cross-over of said word line and said bit line determine the logical state of the cell formed at that cross-over.

Claim 3

Structure as in claim 1 wherein said word lines are comprised of conductive regions of a first width interspersed with selected regions of a second width forming said narrowed width portions at multiple selected cross-overs, said second width being less than said first width.

Claim 4

Structure as in claim 1, wherein said regions of said second width comprise notches and said notches have a U shape.

Claim 5

Structure as in claim 2, wherein said regions of said second width comprise notches and said notches have a rectangular shape.

Claim 6

Structure as in claim 2, wherein cells formed at the cross-overs of bit lines and portions of word lines having said first width are fully functional MOS transistors, and cells formed at the cross-overs of bit lines and said portions of word lines having said second width are always conductive.

Claim 7

Structure as in claim 5 wherein said always conductive cells are formed with a continuous bit line under said portions of said word lines having said second width.

Claim 8

Structure as in claim 2, wherein cells formed at the cross-overs of bit lines and portions of word lines having said first width are fully functional MOS transistors, and cells formed at the cross-overs of bit lines and said portions of said word lines having said second width are transistors having extremely low source to drain punchthrough voltage in the "off" state, and thus will always conduct when read.

Claim 9

A programmed semiconductor memory cell contained in read only memory comprised of a plurality of semiconductor memory cells located on a semiconductor substrate of a first conductivity type, said programmed semiconductor memory cell comprising: an underlying buried region of opposite conductivity type formed in said substrate serving as a bit line; a layer of electrical insulating material covering said bit line; a conductive path having a first width serving as a word line lying substantially perpendicular above said bit line and forming cross-overs therewith, said word line being separated from said bit line by said insulating material, wherein said word line serves as a mask during the formation of said bit line, and the width of said word line at ones of said cross-overs of said bit line being of a second width narrower than said first width, thus forming a cell which is always conductive.

Claim 10

A programmed semiconductor memory cell contained in read only memory comprised of a plurality of semiconductor memory cells located on a semiconductor substrate of a first conductivity type, said programmed semiconductor memory cell comprising: an underlying buried region of opposite conductivity type formed in said substrate serving as a bit line; a layer of electrical insulating material covering said bit line; a conductive path having a first width serving as a word line lying substantially perpendicular above said bit line and forming cross-overs therewith, said word line being separated from said bit line by said insulating material, wherein said word line serves as a mask during the formation of said bit line, and the width of said word line at ones of said cross-overs of said bit line being of a second width narrower than said first width, thus forming a cell which is always conductive.

Claim 11

A serial access MOS ROM comprised of: a semiconductor substrate of a first conductivity type; a plurality of buried regions formed in said substrate serving as bit lines of an opposite conductivity type; a layer of electrical insulating material covering said bit lines; a plurality of conductive paths having nonuniform widths, said plurality of conductive paths serving as word lines lying substantially perpendicular above said bit lines and separated from said bit lines by said insulating material; a plurality of semiconductor memory cells formed at each cross-over of said bit lines and said word lines; wherein said word lines serve as a mask during the formation of said bit lines and the width of each of said word lines at each cross-over of said word line and said bit line determine the logical state of the cell formed at that cross-over; said word lines of nonuniform width comprising conductive regions of a first width interspersed with selected regions of a second width, said second width being less than said first width; and wherein cells formed at the cross-overs of bit lines and portions of word lines having said first width are fully functional MOS transistors, and cells formed at the cross-overs of bit lines and said portions of word lines having said second width are always conductive.

Claim 12

A serial access MOS ROM comprised of: a semiconductor substrate of a first conductivity type; a plurality of buried regions formed in said substrate serving as bit lines of an opposite conductivity type; a layer of electrical insulating material covering said bit lines; a plurality of conductive paths having nonuniform widths, said plurality of conductive paths serving as word lines lying substantially perpendicular above said bit lines and separated from said bit lines by said insulating material; a plurality of semiconductor memory cells formed at each cross-over of said bit lines and said word lines; wherein said word lines serve as a mask during the formation of said bit lines and the width of each of said word lines at each cross-over of said word line and said bit line determine the logical state of the cell formed at that cross-over; said word lines of nonuniform width comprising conductive regions of a first width interspersed with selected regions of a second width, said second width being less than said first width; and wherein cells formed at the cross-overs of bit lines and portions of word lines having said first width are fully functional MOS transistors, and cells formed at the cross-overs of bit lines and said portions of word lines having said second width are always conductive.

Claim 13

Structure as in claim 9 wherein said always conductive cells are formed with a continuous bit line under said portions of said word lines having said second width.

Claim 14

A serial access MOS ROM comprised of: a semiconductor substrate of a first conductivity type; a plurality of buried regions formed in said substrate serving as bit lines of an opposite conductivity type; a layer of electrical insulating material covering said bit lines; a plurality of conductive paths having nonuniform widths, said plurality of conductive paths serving as word lines lying substantially perpendicular above said bit lines and separated from said bit lines by said insulating material; a plurality of semiconductor memory cells formed at each cross-over of said bit lines and said word lines; wherein said word lines serve as a mask during the formation of said bit lines and the width of each of said word lines at each cross-over of said word line and said bit line determine the logical state of the cell formed at that cross-over; said word lines of nonuniform width comprising conductive regions of a first width interspersed with selected regions of a second width, said second width being less than said first width; and wherein cells formed at the cross-overs of bit lines and portions of word lines having said first width are fully functional MOS transistors, and cells formed at the cross-overs of bit lines and said portions of said word lines having said second width are transistors having extremely low source to drain punchthrough voltage in the "off" state, and thus will always conduct when read.

Claim 15

A serial access MOS ROM comprised of: a semiconductor substrate of a first conductivity type; a plurality of buried regions formed in said substrate serving as bit lines of an opposite conductivity type; a layer of electrical insulating material covering said bit lines; a plurality of conductive paths having nonuniform widths, said plurality of conductive paths serving as word lines lying substantially perpendicular above said bit lines and separated from said bit lines by said insulating material; a plurality of semiconductor memory cells formed at each cross-over of said bit lines and said word lines; wherein said word lines serve as a mask during the formation of said bit lines and the width of each of said word lines at each cross-over of said word line and said bit line determine the logical state of the cell formed at that cross-over; said word lines of nonuniform width comprising conductive regions of a first width interspersed with selected regions of a second width, said second width being less than said first width; and wherein cells formed at the cross-overs of bit lines and portions of word lines having said first width are fully functional MOS transistors, and cells formed at the cross-overs of bit lines and said portions of said word lines having said second width are transistors having extremely low source to drain punchthrough voltage in the "off" state, and thus will always conduct when read.